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llvm-mirror/test/CodeGen/X86/test-nofold.ll
Andrew Trick e89c19ab7b In the pre-RA scheduler, maintain cmp+br proximity.
This is done by pushing physical register definitions close to their
use, which happens to handle flag definitions if they're not glued to
the branch. This seems to be generally a good thing though, so I
didn't need to add a target hook yet.

The primary motivation is to generate code closer to what people
expect and rule out missed opportunity from enabling macro-op
fusion. As a side benefit, we get several 2-5% gains on x86
benchmarks. There is one regression:
SingleSource/Benchmarks/Shootout/lists slows down be -10%. But this is
an independent scheduler bug that will be tracked separately.
See rdar://problem/9283108.

Incidentally, pre-RA scheduling is only half the solution. Fixing the
later passes is tracked by:
<rdar://problem/8932804> [pre-RA-sched] on x86, attempt to schedule CMP/TEST adjacent with condition jump

Fixes:
<rdar://problem/9262453> Scheduler unnecessary break of cmp/jump fusion

llvm-svn: 129508
2011-04-14 05:15:06 +00:00

43 lines
915 B
LLVM

; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
; rdar://5752025
; We want:
; CHECK: movl $42, %ecx
; CHECK-NEXT: movl 4(%esp), %eax
; CHECK-NEXT: andl $15, %eax
; CHECK-NEXT: cmovnel %ecx, %eax
; CHECK-NEXT: ret
;
; We don't want:
; movl 4(%esp), %eax
; movl %eax, %ecx # bad: extra copy
; andl $15, %ecx
; testl $15, %eax # bad: peep obstructed
; movl $42, %eax
; cmovel %ecx, %eax
; ret
;
; We also don't want:
; movl $15, %ecx # bad: larger encoding
; andl 4(%esp), %ecx
; movl $42, %eax
; cmovel %ecx, %eax
; ret
;
; We also don't want:
; movl 4(%esp), %ecx
; andl $15, %ecx
; testl %ecx, %ecx # bad: unnecessary test
; movl $42, %eax
; cmovel %ecx, %eax
; ret
define i32 @t1(i32 %X) nounwind {
entry:
%tmp2 = and i32 %X, 15 ; <i32> [#uses=2]
%tmp4 = icmp eq i32 %tmp2, 0 ; <i1> [#uses=1]
%retval = select i1 %tmp4, i32 %tmp2, i32 42 ; <i32> [#uses=1]
ret i32 %retval
}