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e25a1a8f41
First patch in a series adding MC layer support for the Arm Scalable
Matrix Extension.
This patch adds the following features:
sme, sme-i64, sme-f64
The sme-i64 and sme-f64 flags are for the optional I16I64 and F64F64
features.
If a target supports I16I64 then the following instructions are
implemented:
* 64-bit integer ADDHA and ADDVA variants (D105570).
* SMOPA, SMOPS, SUMOPA, SUMOPS, UMOPA, UMOPS, USMOPA, and USMOPS
instructions that accumulate 16-bit integer outer products into 64-bit
integer tiles.
If a target supports F64F64 then the FMOPA and FMOPS instructions that
accumulate double-precision floating-point outer products into
double-precision tiles are implemented.
Outer products are implemented in D105571.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06
Reviewed By: CarolineConcatto
Differential Revision: https://reviews.llvm.org/D105569
621 lines
20 KiB
C++
621 lines
20 KiB
C++
//===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the AArch64 specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
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#include "AArch64FrameLowering.h"
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#include "AArch64ISelLowering.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64RegisterInfo.h"
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#include "AArch64SelectionDAGInfo.h"
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/InlineAsmLowering.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "AArch64GenSubtargetInfo.inc"
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namespace llvm {
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class GlobalValue;
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class StringRef;
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class Triple;
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class AArch64Subtarget final : public AArch64GenSubtargetInfo {
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public:
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enum ARMProcFamilyEnum : uint8_t {
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Others,
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A64FX,
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AppleA7,
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AppleA10,
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AppleA11,
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AppleA12,
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AppleA13,
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AppleA14,
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Carmel,
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CortexA35,
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CortexA53,
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CortexA55,
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CortexA57,
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CortexA65,
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CortexA72,
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CortexA73,
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CortexA75,
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CortexA76,
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CortexA77,
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CortexA78,
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CortexA78C,
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CortexR82,
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CortexX1,
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ExynosM3,
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Falkor,
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Kryo,
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NeoverseE1,
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NeoverseN1,
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NeoverseN2,
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NeoverseV1,
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Saphira,
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ThunderX2T99,
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ThunderX,
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ThunderXT81,
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ThunderXT83,
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ThunderXT88,
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ThunderX3T110,
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TSV110
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};
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protected:
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/// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
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ARMProcFamilyEnum ARMProcFamily = Others;
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bool HasV8_1aOps = false;
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bool HasV8_2aOps = false;
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bool HasV8_3aOps = false;
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bool HasV8_4aOps = false;
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bool HasV8_5aOps = false;
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bool HasV8_6aOps = false;
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bool HasV8_7aOps = false;
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bool HasV8_0rOps = false;
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bool HasCONTEXTIDREL2 = false;
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bool HasFPARMv8 = false;
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bool HasNEON = false;
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bool HasCrypto = false;
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bool HasDotProd = false;
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bool HasCRC = false;
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bool HasLSE = false;
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bool HasRAS = false;
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bool HasRDM = false;
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bool HasPerfMon = false;
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bool HasFullFP16 = false;
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bool HasFP16FML = false;
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bool HasSPE = false;
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// ARMv8.1 extensions
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bool HasVH = false;
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bool HasPAN = false;
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bool HasLOR = false;
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// ARMv8.2 extensions
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bool HasPsUAO = false;
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bool HasPAN_RWV = false;
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bool HasCCPP = false;
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// SVE extensions
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bool HasSVE = false;
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bool UseExperimentalZeroingPseudos = false;
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// Armv8.2 Crypto extensions
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bool HasSM4 = false;
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bool HasSHA3 = false;
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bool HasSHA2 = false;
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bool HasAES = false;
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// ARMv8.3 extensions
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bool HasPAuth = false;
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bool HasJS = false;
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bool HasCCIDX = false;
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bool HasComplxNum = false;
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// ARMv8.4 extensions
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bool HasNV = false;
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bool HasMPAM = false;
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bool HasDIT = false;
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bool HasTRACEV8_4 = false;
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bool HasAM = false;
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bool HasSEL2 = false;
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bool HasPMU = false;
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bool HasTLB_RMI = false;
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bool HasFlagM = false;
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bool HasRCPC_IMMO = false;
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bool HasLSLFast = false;
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bool HasRCPC = false;
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bool HasAggressiveFMA = false;
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// Armv8.5-A Extensions
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bool HasAlternativeNZCV = false;
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bool HasFRInt3264 = false;
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bool HasSpecRestrict = false;
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bool HasSSBS = false;
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bool HasSB = false;
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bool HasPredRes = false;
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bool HasCCDP = false;
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bool HasBTI = false;
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bool HasRandGen = false;
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bool HasMTE = false;
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bool HasTME = false;
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// Armv8.6-A Extensions
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bool HasBF16 = false;
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bool HasMatMulInt8 = false;
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bool HasMatMulFP32 = false;
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bool HasMatMulFP64 = false;
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bool HasAMVS = false;
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bool HasFineGrainedTraps = false;
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bool HasEnhancedCounterVirtualization = false;
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// Armv8.7-A Extensions
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bool HasXS = false;
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bool HasWFxT = false;
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bool HasHCX = false;
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bool HasLS64 = false;
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// Arm SVE2 extensions
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bool HasSVE2 = false;
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bool HasSVE2AES = false;
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bool HasSVE2SM4 = false;
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bool HasSVE2SHA3 = false;
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bool HasSVE2BitPerm = false;
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// Armv9-A Extensions
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bool HasRME = false;
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// Arm Scalable Matrix Extension (SME)
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bool HasSME = false;
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bool HasSMEF64 = false;
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bool HasSMEI64 = false;
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// Future architecture extensions.
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bool HasETE = false;
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bool HasTRBE = false;
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bool HasBRBE = false;
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bool HasPAUTH = false;
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bool HasSPE_EEF = false;
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// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
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bool HasZeroCycleRegMove = false;
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// HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
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bool HasZeroCycleZeroing = false;
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bool HasZeroCycleZeroingGP = false;
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bool HasZeroCycleZeroingFPWorkaround = false;
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// It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0".
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// as movi is more efficient across all cores. Newer cores can eliminate
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// fmovs early and there is no difference with movi, but this not true for
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// all implementations.
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bool HasZeroCycleZeroingFP = true;
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// StrictAlign - Disallow unaligned memory accesses.
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bool StrictAlign = false;
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// NegativeImmediates - transform instructions with negative immediates
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bool NegativeImmediates = true;
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// Enable 64-bit vectorization in SLP.
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unsigned MinVectorRegisterBitWidth = 64;
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bool OutlineAtomics = false;
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bool PredictableSelectIsExpensive = false;
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bool BalanceFPOps = false;
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bool CustomAsCheapAsMove = false;
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bool ExynosAsCheapAsMove = false;
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bool UsePostRAScheduler = false;
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bool Misaligned128StoreIsSlow = false;
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bool Paired128IsSlow = false;
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bool STRQroIsSlow = false;
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bool UseAlternateSExtLoadCVTF32Pattern = false;
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bool HasArithmeticBccFusion = false;
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bool HasArithmeticCbzFusion = false;
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bool HasCmpBccFusion = false;
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bool HasFuseAddress = false;
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bool HasFuseAES = false;
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bool HasFuseArithmeticLogic = false;
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bool HasFuseCCSelect = false;
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bool HasFuseCryptoEOR = false;
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bool HasFuseLiterals = false;
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bool DisableLatencySchedHeuristic = false;
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bool UseRSqrt = false;
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bool Force32BitJumpTables = false;
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bool UseEL1ForTP = false;
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bool UseEL2ForTP = false;
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bool UseEL3ForTP = false;
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bool AllowTaggedGlobals = false;
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bool HardenSlsRetBr = false;
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bool HardenSlsBlr = false;
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bool HardenSlsNoComdat = false;
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uint8_t MaxInterleaveFactor = 2;
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uint8_t VectorInsertExtractBaseCost = 3;
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uint16_t CacheLineSize = 0;
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uint16_t PrefetchDistance = 0;
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uint16_t MinPrefetchStride = 1;
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unsigned MaxPrefetchIterationsAhead = UINT_MAX;
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unsigned PrefFunctionLogAlignment = 0;
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unsigned PrefLoopLogAlignment = 0;
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unsigned MaxJumpTableSize = 0;
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unsigned WideningBaseCost = 0;
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// ReserveXRegister[i] - X#i is not available as a general purpose register.
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BitVector ReserveXRegister;
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// CustomCallUsedXRegister[i] - X#i call saved.
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BitVector CustomCallSavedXRegs;
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bool IsLittle;
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unsigned MinSVEVectorSizeInBits;
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unsigned MaxSVEVectorSizeInBits;
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/// TargetTriple - What processor and OS we're targeting.
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Triple TargetTriple;
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AArch64FrameLowering FrameLowering;
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AArch64InstrInfo InstrInfo;
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AArch64SelectionDAGInfo TSInfo;
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AArch64TargetLowering TLInfo;
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/// GlobalISel related APIs.
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std::unique_ptr<CallLowering> CallLoweringInfo;
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std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
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std::unique_ptr<InstructionSelector> InstSelector;
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std::unique_ptr<LegalizerInfo> Legalizer;
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std::unique_ptr<RegisterBankInfo> RegBankInfo;
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private:
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/// initializeSubtargetDependencies - Initializes using CPUString and the
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/// passed in feature string so that we can use initializer lists for
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/// subtarget initialization.
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AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
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StringRef CPUString);
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/// Initialize properties based on the selected processor family.
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void initializeProperties();
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public:
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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AArch64Subtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS, const TargetMachine &TM,
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bool LittleEndian,
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unsigned MinSVEVectorSizeInBitsOverride = 0,
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unsigned MaxSVEVectorSizeInBitsOverride = 0);
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const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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const AArch64FrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const AArch64TargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const AArch64RegisterInfo *getRegisterInfo() const override {
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return &getInstrInfo()->getRegisterInfo();
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}
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const CallLowering *getCallLowering() const override;
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const InlineAsmLowering *getInlineAsmLowering() const override;
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InstructionSelector *getInstructionSelector() const override;
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const LegalizerInfo *getLegalizerInfo() const override;
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const RegisterBankInfo *getRegBankInfo() const override;
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const Triple &getTargetTriple() const { return TargetTriple; }
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bool enableMachineScheduler() const override { return true; }
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bool enablePostRAScheduler() const override {
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return UsePostRAScheduler;
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}
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/// Returns ARM processor family.
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/// Avoid this function! CPU specifics should be kept local to this class
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/// and preferably modeled with SubtargetFeatures or properties in
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/// initializeProperties().
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ARMProcFamilyEnum getProcFamily() const {
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return ARMProcFamily;
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}
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bool hasV8_1aOps() const { return HasV8_1aOps; }
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bool hasV8_2aOps() const { return HasV8_2aOps; }
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bool hasV8_3aOps() const { return HasV8_3aOps; }
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bool hasV8_4aOps() const { return HasV8_4aOps; }
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bool hasV8_5aOps() const { return HasV8_5aOps; }
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bool hasV8_0rOps() const { return HasV8_0rOps; }
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bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
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bool hasZeroCycleZeroingGP() const { return HasZeroCycleZeroingGP; }
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bool hasZeroCycleZeroingFP() const { return HasZeroCycleZeroingFP; }
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bool hasZeroCycleZeroingFPWorkaround() const {
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return HasZeroCycleZeroingFPWorkaround;
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}
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bool requiresStrictAlign() const { return StrictAlign; }
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bool isXRaySupported() const override { return true; }
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unsigned getMinVectorRegisterBitWidth() const {
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return MinVectorRegisterBitWidth;
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}
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bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
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unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
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bool isXRegCustomCalleeSaved(size_t i) const {
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return CustomCallSavedXRegs[i];
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}
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bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
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bool hasFPARMv8() const { return HasFPARMv8; }
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bool hasNEON() const { return HasNEON; }
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bool hasCrypto() const { return HasCrypto; }
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bool hasDotProd() const { return HasDotProd; }
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bool hasCRC() const { return HasCRC; }
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bool hasLSE() const { return HasLSE; }
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bool hasRAS() const { return HasRAS; }
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bool hasRDM() const { return HasRDM; }
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bool hasSM4() const { return HasSM4; }
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bool hasSHA3() const { return HasSHA3; }
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bool hasSHA2() const { return HasSHA2; }
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bool hasAES() const { return HasAES; }
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bool hasCONTEXTIDREL2() const { return HasCONTEXTIDREL2; }
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bool balanceFPOps() const { return BalanceFPOps; }
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bool predictableSelectIsExpensive() const {
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return PredictableSelectIsExpensive;
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}
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bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
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bool hasExynosCheapAsMoveHandling() const { return ExynosAsCheapAsMove; }
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bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
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bool isPaired128Slow() const { return Paired128IsSlow; }
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bool isSTRQroSlow() const { return STRQroIsSlow; }
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bool useAlternateSExtLoadCVTF32Pattern() const {
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return UseAlternateSExtLoadCVTF32Pattern;
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}
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bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
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bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
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bool hasCmpBccFusion() const { return HasCmpBccFusion; }
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bool hasFuseAddress() const { return HasFuseAddress; }
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bool hasFuseAES() const { return HasFuseAES; }
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bool hasFuseArithmeticLogic() const { return HasFuseArithmeticLogic; }
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bool hasFuseCCSelect() const { return HasFuseCCSelect; }
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bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
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bool hasFuseLiterals() const { return HasFuseLiterals; }
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/// Return true if the CPU supports any kind of instruction fusion.
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bool hasFusion() const {
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return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
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hasFuseAES() || hasFuseArithmeticLogic() ||
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hasFuseCCSelect() || hasFuseLiterals();
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}
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bool hardenSlsRetBr() const { return HardenSlsRetBr; }
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bool hardenSlsBlr() const { return HardenSlsBlr; }
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bool hardenSlsNoComdat() const { return HardenSlsNoComdat; }
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bool useEL1ForTP() const { return UseEL1ForTP; }
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bool useEL2ForTP() const { return UseEL2ForTP; }
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bool useEL3ForTP() const { return UseEL3ForTP; }
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bool useRSqrt() const { return UseRSqrt; }
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bool force32BitJumpTables() const { return Force32BitJumpTables; }
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unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
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unsigned getVectorInsertExtractBaseCost() const {
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return VectorInsertExtractBaseCost;
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}
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unsigned getCacheLineSize() const override { return CacheLineSize; }
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unsigned getPrefetchDistance() const override { return PrefetchDistance; }
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unsigned getMinPrefetchStride(unsigned NumMemAccesses,
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unsigned NumStridedMemAccesses,
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unsigned NumPrefetches,
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bool HasCall) const override {
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return MinPrefetchStride;
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}
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unsigned getMaxPrefetchIterationsAhead() const override {
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return MaxPrefetchIterationsAhead;
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}
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unsigned getPrefFunctionLogAlignment() const {
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return PrefFunctionLogAlignment;
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}
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unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
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unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
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unsigned getWideningBaseCost() const { return WideningBaseCost; }
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bool useExperimentalZeroingPseudos() const {
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return UseExperimentalZeroingPseudos;
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}
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/// CPU has TBI (top byte of addresses is ignored during HW address
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/// translation) and OS enables it.
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bool supportsAddressTopByteIgnored() const;
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bool hasPerfMon() const { return HasPerfMon; }
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bool hasFullFP16() const { return HasFullFP16; }
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bool hasFP16FML() const { return HasFP16FML; }
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bool hasSPE() const { return HasSPE; }
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bool hasLSLFast() const { return HasLSLFast; }
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bool hasSVE() const { return HasSVE; }
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bool hasSVE2() const { return HasSVE2; }
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bool hasRCPC() const { return HasRCPC; }
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bool hasAggressiveFMA() const { return HasAggressiveFMA; }
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bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
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bool hasFRInt3264() const { return HasFRInt3264; }
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bool hasSpecRestrict() const { return HasSpecRestrict; }
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bool hasSSBS() const { return HasSSBS; }
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bool hasSB() const { return HasSB; }
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|
bool hasPredRes() const { return HasPredRes; }
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|
bool hasCCDP() const { return HasCCDP; }
|
|
bool hasBTI() const { return HasBTI; }
|
|
bool hasRandGen() const { return HasRandGen; }
|
|
bool hasMTE() const { return HasMTE; }
|
|
bool hasTME() const { return HasTME; }
|
|
bool hasPAUTH() const { return HasPAUTH; }
|
|
// Arm SVE2 extensions
|
|
bool hasSVE2AES() const { return HasSVE2AES; }
|
|
bool hasSVE2SM4() const { return HasSVE2SM4; }
|
|
bool hasSVE2SHA3() const { return HasSVE2SHA3; }
|
|
bool hasSVE2BitPerm() const { return HasSVE2BitPerm; }
|
|
bool hasMatMulInt8() const { return HasMatMulInt8; }
|
|
bool hasMatMulFP32() const { return HasMatMulFP32; }
|
|
bool hasMatMulFP64() const { return HasMatMulFP64; }
|
|
|
|
// Armv8.6-A Extensions
|
|
bool hasBF16() const { return HasBF16; }
|
|
bool hasFineGrainedTraps() const { return HasFineGrainedTraps; }
|
|
bool hasEnhancedCounterVirtualization() const {
|
|
return HasEnhancedCounterVirtualization;
|
|
}
|
|
|
|
// Arm Scalable Matrix Extension (SME)
|
|
bool hasSME() const { return HasSME; }
|
|
bool hasSMEF64() const { return HasSMEF64; }
|
|
bool hasSMEI64() const { return HasSMEI64; }
|
|
|
|
bool isLittleEndian() const { return IsLittle; }
|
|
|
|
bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
|
|
bool isTargetIOS() const { return TargetTriple.isiOS(); }
|
|
bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
|
|
bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
|
|
bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
|
|
bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
|
|
|
|
bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
|
|
bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
|
|
bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
|
|
|
|
bool isTargetILP32() const {
|
|
return TargetTriple.isArch32Bit() ||
|
|
TargetTriple.getEnvironment() == Triple::GNUILP32;
|
|
}
|
|
|
|
bool useAA() const override;
|
|
|
|
bool outlineAtomics() const { return OutlineAtomics; }
|
|
|
|
bool hasVH() const { return HasVH; }
|
|
bool hasPAN() const { return HasPAN; }
|
|
bool hasLOR() const { return HasLOR; }
|
|
|
|
bool hasPsUAO() const { return HasPsUAO; }
|
|
bool hasPAN_RWV() const { return HasPAN_RWV; }
|
|
bool hasCCPP() const { return HasCCPP; }
|
|
|
|
bool hasPAuth() const { return HasPAuth; }
|
|
bool hasJS() const { return HasJS; }
|
|
bool hasCCIDX() const { return HasCCIDX; }
|
|
bool hasComplxNum() const { return HasComplxNum; }
|
|
|
|
bool hasNV() const { return HasNV; }
|
|
bool hasMPAM() const { return HasMPAM; }
|
|
bool hasDIT() const { return HasDIT; }
|
|
bool hasTRACEV8_4() const { return HasTRACEV8_4; }
|
|
bool hasAM() const { return HasAM; }
|
|
bool hasAMVS() const { return HasAMVS; }
|
|
bool hasXS() const { return HasXS; }
|
|
bool hasWFxT() const { return HasWFxT; }
|
|
bool hasHCX() const { return HasHCX; }
|
|
bool hasLS64() const { return HasLS64; }
|
|
bool hasSEL2() const { return HasSEL2; }
|
|
bool hasPMU() const { return HasPMU; }
|
|
bool hasTLB_RMI() const { return HasTLB_RMI; }
|
|
bool hasFlagM() const { return HasFlagM; }
|
|
bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
|
|
|
|
bool addrSinkUsingGEPs() const override {
|
|
// Keeping GEPs inbounds is important for exploiting AArch64
|
|
// addressing-modes in ILP32 mode.
|
|
return useAA() || isTargetILP32();
|
|
}
|
|
|
|
bool useSmallAddressing() const {
|
|
switch (TLInfo.getTargetMachine().getCodeModel()) {
|
|
case CodeModel::Kernel:
|
|
// Kernel is currently allowed only for Fuchsia targets,
|
|
// where it is the same as Small for almost all purposes.
|
|
case CodeModel::Small:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
/// ParseSubtargetFeatures - Parses features string setting specified
|
|
/// subtarget options. Definition of function is auto generated by tblgen.
|
|
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
|
|
|
|
/// ClassifyGlobalReference - Find the target operand flags that describe
|
|
/// how a global value should be referenced for the current subtarget.
|
|
unsigned ClassifyGlobalReference(const GlobalValue *GV,
|
|
const TargetMachine &TM) const;
|
|
|
|
unsigned classifyGlobalFunctionReference(const GlobalValue *GV,
|
|
const TargetMachine &TM) const;
|
|
|
|
void overrideSchedPolicy(MachineSchedPolicy &Policy,
|
|
unsigned NumRegionInstrs) const override;
|
|
|
|
bool enableEarlyIfConversion() const override;
|
|
|
|
bool enableAdvancedRASplitCost() const override { return false; }
|
|
|
|
std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
|
|
|
|
bool isCallingConvWin64(CallingConv::ID CC) const {
|
|
switch (CC) {
|
|
case CallingConv::C:
|
|
case CallingConv::Fast:
|
|
case CallingConv::Swift:
|
|
return isTargetWindows();
|
|
case CallingConv::Win64:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
void mirFileLoaded(MachineFunction &MF) const override;
|
|
|
|
// Return the known range for the bit length of SVE data registers. A value
|
|
// of 0 means nothing is known about that particular limit beyong what's
|
|
// implied by the architecture.
|
|
unsigned getMaxSVEVectorSizeInBits() const {
|
|
assert(HasSVE && "Tried to get SVE vector length without SVE support!");
|
|
return MaxSVEVectorSizeInBits;
|
|
}
|
|
|
|
unsigned getMinSVEVectorSizeInBits() const {
|
|
assert(HasSVE && "Tried to get SVE vector length without SVE support!");
|
|
return MinSVEVectorSizeInBits;
|
|
}
|
|
|
|
bool useSVEForFixedLengthVectors() const;
|
|
};
|
|
} // End llvm namespace
|
|
|
|
#endif
|