Craig Topper 2c18b0ad47 [X86] Correct scheduler information for rotate by constant for Haswell, Broadwell, and Skylake. ...

Rotate with explicit immediate is a single uop from Haswell on. An immediate of 1 has a dependency on the previous writer of flags, but the other immediate values do not.

The implicit rotate by 1 instruction is 2 uops. But the flags are merged after the rotate uop so the data result does not see the flag dependency. But I don't think we have any way of modeling that.

RORX is 1 uop without the load. 2 uops with the load. We currently model these with WriteShift/WriteShiftLd.

Differential Revision: https://reviews.llvm.org/D59077

llvm-svn: 355636

2019-03-07 21:22:56 +00:00

..

AArch64

[llvm-mca] Update tests for Exynos (NFC)

2019-01-11 19:36:27 +00:00

ARM

[llvm-mca] Add support for instructions with a variadic number of operands.

2018-11-25 12:46:24 +00:00

SystemZ

[MCA] Add support for BeginGroup/EndGroup.

2018-12-17 14:27:33 +00:00

X86

[X86] Correct scheduler information for rotate by constant for Haswell, Broadwell, and Skylake.

2019-03-07 21:22:56 +00:00

invalid_input_file_name.test

Replace unused output filenames with /dev/null in tests

2018-07-02 18:16:44 +00:00

lit.local.cfg

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