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llvm-mirror/test/CodeGen/NVPTX/fma-disable.ll
Justin Holewinski 4ca961430f This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it.
The new target machines are:

nvptx (old ptx32) => 32-bit PTX
nvptx64 (old ptx64) => 64-bit PTX

The sources are based on the internal NVIDIA NVPTX back-end, and
contain more functionality than the current PTX back-end currently
provides.

NV_CONTRIB

llvm-svn: 156196
2012-05-04 20:18:50 +00:00

25 lines
785 B
LLVM

; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA
; RUN: llc < %s -march=nvptx -mcpu=sm_20 -nvptx-fma-level=0 | FileCheck %s -check-prefix=MUL
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=1 | FileCheck %s -check-prefix=FMA
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-fma-level=0 | FileCheck %s -check-prefix=MUL
define ptx_device float @test_mul_add_f(float %x, float %y, float %z) {
entry:
; FMA: fma.rn.f32
; MUL: mul.rn.f32
; MUL: add.rn.f32
%a = fmul float %x, %y
%b = fadd float %a, %z
ret float %b
}
define ptx_device double @test_mul_add_d(double %x, double %y, double %z) {
entry:
; FMA: fma.rn.f64
; MUL: mul.rn.f64
; MUL: add.rn.f64
%a = fmul double %x, %y
%b = fadd double %a, %z
ret double %b
}