mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-29 23:12:55 +01:00
60e9ada729
The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
20 lines
460 B
LLVM
20 lines
460 B
LLVM
; RUN: llc < %s -mcpu=corei7 -march=x86 -verify-machineinstrs | FileCheck %s
|
|
|
|
; 64-bit load/store on x86-32
|
|
; FIXME: The generated code can be substantially improved.
|
|
|
|
define void @test1(i64* %ptr, i64 %val1) {
|
|
; CHECK: test1
|
|
; CHECK: cmpxchg8b
|
|
; CHECK-NEXT: jne
|
|
store atomic i64 %val1, i64* %ptr seq_cst, align 8
|
|
ret void
|
|
}
|
|
|
|
define i64 @test2(i64* %ptr) {
|
|
; CHECK: test2
|
|
; CHECK: cmpxchg8b
|
|
%val = load atomic i64* %ptr seq_cst, align 8
|
|
ret i64 %val
|
|
}
|