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f7aeb57c87
On targets without cmpxchg16b or cmpxchg8b, the borderline atomic operations were slipping through the gaps. X86AtomicExpand.cpp was delegating to ISelLowering. Generic ISelLowering was delegating to X86ISelLowering and X86ISelLowering was asserting. The correct behaviour is to expand to a libcall, preferably in generic ISelLowering. This can be achieved by X86ISelLowering deciding it doesn't want the faff after all. llvm-svn: 212134
44 lines
1.1 KiB
LLVM
44 lines
1.1 KiB
LLVM
; RUN: llc -mtriple=i386-linux-gnu %s -o - | FileCheck %s
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define i64 @test_add(i64* %addr, i64 %inc) {
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; CHECK-LABEL: test_add:
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; CHECK: calll __sync_fetch_and_add_8
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%old = atomicrmw add i64* %addr, i64 %inc seq_cst
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ret i64 %old
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}
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define i64 @test_sub(i64* %addr, i64 %inc) {
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; CHECK-LABEL: test_sub:
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; CHECK: calll __sync_fetch_and_sub_8
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%old = atomicrmw sub i64* %addr, i64 %inc seq_cst
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ret i64 %old
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}
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define i64 @test_and(i64* %andr, i64 %inc) {
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; CHECK-LABEL: test_and:
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; CHECK: calll __sync_fetch_and_and_8
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%old = atomicrmw and i64* %andr, i64 %inc seq_cst
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ret i64 %old
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}
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define i64 @test_or(i64* %orr, i64 %inc) {
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; CHECK-LABEL: test_or:
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; CHECK: calll __sync_fetch_and_or_8
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%old = atomicrmw or i64* %orr, i64 %inc seq_cst
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ret i64 %old
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}
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define i64 @test_xor(i64* %xorr, i64 %inc) {
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; CHECK-LABEL: test_xor:
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; CHECK: calll __sync_fetch_and_xor_8
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%old = atomicrmw xor i64* %xorr, i64 %inc seq_cst
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ret i64 %old
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}
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define i64 @test_nand(i64* %nandr, i64 %inc) {
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; CHECK-LABEL: test_nand:
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; CHECK: calll __sync_fetch_and_nand_8
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%old = atomicrmw nand i64* %nandr, i64 %inc seq_cst
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ret i64 %old
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}
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