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c5d78d63ff
MIsNeedChainEdge, which is used by -enable-aa-sched-mi (AA in misched), had an llvm_unreachable when -enable-aa-sched-mi is enabled and we reach an instruction with multiple MMOs. Instead, return a conservative answer. This allows testing -enable-aa-sched-mi on x86. Also, this moves the check above the isUnsafeMemoryObject checks. isUnsafeMemoryObject is currently correct only for instructions with one MMO (as noted in the comment in isUnsafeMemoryObject): // We purposefully do no check for hasOneMemOperand() here // in hope to trigger an assert downstream in order to // finish implementation. The problem with this is that, had the candidate edge passed the "!MIa->mayStore() && !MIb->mayStore()" check, the hoped-for assert would never happen (which could, in theory, lead to incorrect behavior if one of these secondary MMOs was volatile, for example). llvm-svn: 198795
38 lines
1.0 KiB
LLVM
38 lines
1.0 KiB
LLVM
; RUN: llc -enable-misched -enable-aa-sched-mi < %s
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; This generates a decw instruction, which has two MMOs, and an alias SU edge
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; query involving that instruction. Make sure this does not crash.
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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%s1 = type { i16, i16, i32 }
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%c1 = type { %s1*, %u1, i16, i8 }
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%u1 = type { i64 }
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declare zeroext i1 @bar(i64*, i32) #5
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define i32 @foo() #0 align 2 {
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entry:
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%temp_rhs = alloca %c1, align 8
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br i1 undef, label %if.else56, label %cond.end.i
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cond.end.i:
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%significand.i18.i = getelementptr inbounds %c1* %temp_rhs, i64 0, i32 1
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%exponent.i = getelementptr inbounds %c1* %temp_rhs, i64 0, i32 2
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%0 = load i16* %exponent.i, align 8
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%sub.i = add i16 %0, -1
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store i16 %sub.i, i16* %exponent.i, align 8
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%parts.i.i = bitcast %u1* %significand.i18.i to i64**
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%1 = load i64** %parts.i.i, align 8
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%call5.i = call zeroext i1 @bar(i64* %1, i32 undef) #1
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unreachable
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if.else56:
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unreachable
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}
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attributes #0 = { nounwind uwtable }
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attributes #1 = { nounwind }
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