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dd18739c8d
Reapply r346374 with the fixes for modules build. Original summary: This change implements assembler parser, code emitter, ELF object writer and disassembler for the MSP430 ISA. Also, more instruction forms are added to the target description. Patch by Michael Skvortsov! llvm-svn: 346948
111 lines
3.6 KiB
ArmAsm
111 lines
3.6 KiB
ArmAsm
; RUN: llvm-mc -triple msp430 -show-encoding < %s | FileCheck %s
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foo:
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mov r8, r15
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mov disp+2(r8), r15
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mov disp+2, r15
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mov &disp+2, r15
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mov @r8, r15
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mov @r8+, r15
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mov #disp+2, r15
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; CHECK: mov r8, r15 ; encoding: [0x0f,0x48]
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; CHECK: mov disp+2(r8), r15 ; encoding: [0x1f,0x48,A,A]
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; CHECK: mov disp+2, r15 ; encoding: [0x1f,0x40,A,A]
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; CHECK: mov &disp+2, r15 ; encoding: [0x1f,0x42,A,A]
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; CHECK: mov @r8, r15 ; encoding: [0x2f,0x48]
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; CHECK: mov @r8+, r15 ; encoding: [0x3f,0x48]
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; CHECK: mov #disp+2, r15 ; encoding: [0x3f,0x40,A,A]
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mov #42, r15
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mov #42, 12(r15)
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mov #42, &disp
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mov disp, disp+2
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; CHECK: mov #42, r15 ; encoding: [0x3f,0x40,0x2a,0x00]
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; CHECK: mov #42, 12(r15) ; encoding: [0xbf,0x40,0x2a,0x00,0x0c,0x00]
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; CHECK: mov #42, &disp ; encoding: [0xb2,0x40,0x2a,0x00,A,A]
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; CHECK: mov disp, disp+2 ; encoding: [0x90,0x40,A,A,B,B]
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add r7, r8
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add 6(r7), r8
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add &disp, r8
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add disp, r8
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add @r9, r8
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add @r9+, r8
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add #42, r8
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; CHECK: add r7, r8 ; encoding: [0x08,0x57]
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; CHECK: add 6(r7), r8 ; encoding: [0x18,0x57,0x06,0x00]
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; CHECK: add &disp, r8 ; encoding: [0x18,0x52,A,A]
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; CHECK: add disp, r8 ; encoding: [0x18,0x50,A,A]
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; CHECK: add @r9, r8 ; encoding: [0x28,0x59]
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; CHECK: add @r9+, r8 ; encoding: [0x38,0x59]
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; CHECK: add #42, r8 ; encoding: [0x38,0x50,0x2a,0x00]
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add r7, 6(r5)
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add 6(r7), 6(r5)
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add &disp, 6(r5)
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add disp, 6(r5)
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add @r9, 6(r5)
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add @r9+, 6(r5)
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add #42, 6(r5)
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; CHECK: add r7, 6(r5) ; encoding: [0x85,0x57,0x06,0x00]
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; CHECK: add 6(r7), 6(r5) ; encoding: [0x95,0x57,0x06,0x00,0x06,0x00]
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; CHECK: add &disp, 6(r5) ; encoding: [0x95,0x52,A,A,0x06,0x00]
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; CHECK: add disp, 6(r5) ; encoding: [0x95,0x50,A,A,0x06,0x00]
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; CHECK: add @r9, 6(r5) ; encoding: [0xa5,0x59,0x06,0x00]
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; CHECK: add @r9+, 6(r5) ; encoding: [0xb5,0x59,0x06,0x00]
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; CHECK: add #42, 6(r5) ; encoding: [0xb5,0x50,0x2a,0x00,0x06,0x00]
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add r7, &disp
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add 6(r7), &disp
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add &disp, &disp
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add disp, &disp
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add @r9, &disp
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add @r9+, &disp
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add #42, &disp
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; CHECK: add r7, &disp ; encoding: [0x82,0x57,A,A]
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; CHECK: add 6(r7), &disp ; encoding: [0x92,0x57,0x06,0x00,A,A]
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; CHECK: add &disp, &disp ; encoding: [0x92,0x52,A,A,B,B]
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; CHECK: add disp, &disp ; encoding: [0x92,0x50,A,A,B,B]
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; CHECK: add @r9, &disp ; encoding: [0xa2,0x59,A,A]
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; CHECK: add @r9+, &disp ; encoding: [0xb2,0x59,A,A]
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; CHECK: add #42, &disp ; encoding: [0xb2,0x50,0x2a,0x00,A,A]
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add r7, disp
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add 6(r7), disp
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add &disp, disp
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add disp, disp
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add @r9, disp
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add @r9+, disp
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add #42, disp
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; CHECK: add r7, disp ; encoding: [0x80,0x57,A,A]
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; CHECK: add 6(r7), disp ; encoding: [0x90,0x57,0x06,0x00,A,A]
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; CHECK: add &disp, disp ; encoding: [0x90,0x52,A,A,B,B]
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; CHECK: add disp, disp ; encoding: [0x90,0x50,A,A,B,B]
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; CHECK: add @r9, disp ; encoding: [0xa0,0x59,A,A]
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; CHECK: add @r9+, disp ; encoding: [0xb0,0x59,A,A]
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; CHECK: add #42, disp ; encoding: [0xb0,0x50,0x2a,0x00,A,A]
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call r7
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call 6(r7)
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call disp+6(r7)
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call &disp
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call disp
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call #disp
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; CHECK: call r7 ; encoding: [0x87,0x12]
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; CHECK: call 6(r7) ; encoding: [0x97,0x12,0x06,0x00]
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; CHECK: call disp+6(r7) ; encoding: [0x97,0x12,A,A]
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; CHECK: call &disp ; encoding: [0x92,0x12,A,A]
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; CHECK: call disp ; encoding: [0x90,0x12,A,A]
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; CHECK: call #disp ; encoding: [0xb0,0x12,A,A]
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disp:
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.word 0xcafe
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.word 0xbabe
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