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dd18739c8d
Reapply r346374 with the fixes for modules build. Original summary: This change implements assembler parser, code emitter, ELF object writer and disassembler for the MSP430 ISA. Also, more instruction forms are added to the target description. Patch by Michael Skvortsov! llvm-svn: 346948
164 lines
6.6 KiB
ArmAsm
164 lines
6.6 KiB
ArmAsm
; RUN: llvm-mc -triple msp430 -show-encoding %s \
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; RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
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; RUN: llvm-mc -triple msp430 -filetype=obj %s \
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; RUN: | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
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;; IForm8 instructions
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mov.b r7, r8 ; CHECK-INST: mov.b r7, r8
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; CHECK: encoding: [0x48,0x47]
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add.b r7, r8 ; CHECK-INST: add.b r7, r8
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; CHECK: encoding: [0x48,0x57]
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addc.b r7, r8 ; CHECK-INST: addc.b r7, r8
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; CHECK: encoding: [0x48,0x67]
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subc.b r7, r8 ; CHECK-INST: subc.b r7, r8
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; CHECK: encoding: [0x48,0x77]
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sub.b r7, r8 ; CHECK-INST: sub.b r7, r8
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; CHECK: encoding: [0x48,0x87]
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cmp.b r7, r8 ; CHECK-INST: cmp.b r7, r8
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; CHECK: encoding: [0x48,0x97]
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dadd.b r7, r8 ; CHECK-INST: dadd.b r7, r8
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; CHECK: encoding: [0x48,0xa7]
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bit.b r7, r8 ; CHECK-INST: bit.b r7, r8
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; CHECK: encoding: [0x48,0xb7]
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bic.b r7, r8 ; CHECK-INST: bic.b r7, r8
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; CHECK: encoding: [0x48,0xc7]
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bis.b r7, r8 ; CHECK-INST: bis.b r7, r8
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; CHECK: encoding: [0x48,0xd7]
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xor.b r7, r8 ; CHECK-INST: xor.b r7, r8
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; CHECK: encoding: [0x48,0xe7]
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and.b r7, r8 ; CHECK-INST: and.b r7, r8
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; CHECK: encoding: [0x48,0xf7]
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;; IForm16 instructions
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mov r7, r8 ; CHECK-INST: mov r7, r8
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; CHECK: encoding: [0x08,0x47]
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add r7, r8 ; CHECK-INST: add r7, r8
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; CHECK: encoding: [0x08,0x57]
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addc r7, r8 ; CHECK-INST: addc r7, r8
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; CHECK: encoding: [0x08,0x67]
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subc r7, r8 ; CHECK-INST: subc r7, r8
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; CHECK: encoding: [0x08,0x77]
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sub r7, r8 ; CHECK-INST: sub r7, r8
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; CHECK: encoding: [0x08,0x87]
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cmp r7, r8 ; CHECK-INST: cmp r7, r8
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; CHECK: encoding: [0x08,0x97]
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dadd r7, r8 ; CHECK-INST: dadd r7, r8
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; CHECK: encoding: [0x08,0xa7]
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bit r7, r8 ; CHECK-INST: bit r7, r8
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; CHECK: encoding: [0x08,0xb7]
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bic r7, r8 ; CHECK-INST: bic r7, r8
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; CHECK: encoding: [0x08,0xc7]
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bis r7, r8 ; CHECK-INST: bis r7, r8
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; CHECK: encoding: [0x08,0xd7]
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xor r7, r8 ; CHECK-INST: xor r7, r8
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; CHECK: encoding: [0x08,0xe7]
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and r7, r8 ; CHECK-INST: and r7, r8
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; CHECK: encoding: [0x08,0xf7]
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;; IIForm8 instructions
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rrc.b r7 ; CHECK-INST: rrc.b r7
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; CHECK: encoding: [0x47,0x10]
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rra.b r7 ; CHECK-INST: rra.b r7
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; CHECK: encoding: [0x47,0x11]
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push.b r7 ; CHECK-INST: push.b r7
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; CHECK: encoding: [0x47,0x12]
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;; IIForm16 instructions
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rrc r7 ; CHECK-INST: rrc r7
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; CHECK: encoding: [0x07,0x10]
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swpb r7 ; CHECK-INST: swpb r7
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; CHECK: encoding: [0x87,0x10]
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rra r7 ; CHECK-INST: rra r7
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; CHECK: encoding: [0x07,0x11]
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sxt r7 ; CHECK-INST: sxt r7
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; CHECK: encoding: [0x87,0x11]
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push r7 ; CHECK-INST: push r7
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; CHECK: encoding: [0x07,0x12]
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call r7 ; CHECK-INST: call r7
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; CHECK: encoding: [0x87,0x12]
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reti ; CHECK-INST: reti
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; CHECK: encoding: [0x00,0x13]
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;; CJForm instructions
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jnz -2 ; CHECK-INST: jne $-2
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; CHECK: encoding: [0xfe,0x23]
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jne -2 ; CHECK-INST: jne $-2
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; CHECK: encoding: [0xfe,0x23]
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jeq -2 ; CHECK-INST: jeq $-2
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; CHECK: encoding: [0xfe,0x27]
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jz -2 ; CHECK-INST: jeq $-2
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; CHECK: encoding: [0xfe,0x27]
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jnc -2 ; CHECK-INST: jlo $-2
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; CHECK: encoding: [0xfe,0x2b]
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jlo -2 ; CHECK-INST: jlo $-2
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; CHECK: encoding: [0xfe,0x2b]
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jc -2 ; CHECK-INST: jhs $-2
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; CHECK: encoding: [0xfe,0x2f]
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jhs -2 ; CHECK-INST: jhs $-2
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; CHECK: encoding: [0xfe,0x2f]
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jn -2 ; CHECK-INST: jn $-2
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; CHECK: encoding: [0xfe,0x33]
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jge -2 ; CHECK-INST: jge $-2
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; CHECK: encoding: [0xfe,0x37]
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jl -2 ; CHECK-INST: jl $-2
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; CHECK: encoding: [0xfe,0x3b]
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jmp $-2 ; CHECK-INST: jmp $-2
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; CHECK: encoding: [0xfe,0x3f]
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;; Emulated arithmetic instructions
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adc r7 ; CHECK-INST: adc r7
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; CHECK: encoding: [0x07,0x63]
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dadc r7 ; CHECK-INST: dadc r7
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; CHECK: encoding: [0x07,0xa3]
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dec r7 ; CHECK-INST: dec r7
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; CHECK: encoding: [0x17,0x83]
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decd r7 ; CHECK-INST: decd r7
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; CHECK: encoding: [0x27,0x83]
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inc r7 ; CHECK-INST: inc r7
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; CHECK: encoding: [0x17,0x53]
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incd r7 ; CHECK-INST: incd r7
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; CHECK: encoding: [0x27,0x53]
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sbc r7 ; CHECK-INST: sbc r7
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; CHECK: encoding: [0x07,0x73]
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;; Emulated logical instructions
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inv r7 ; CHECK-INST: inv r7
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; CHECK: encoding: [0x37,0xe3]
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rla r7 ; CHECK-INST: add r7, r7
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; CHECK: encoding: [0x07,0x57]
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rlc r7 ; CHECK-INST: addc r7, r7
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; CHECK: encoding: [0x07,0x67]
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;; Emulated program flow control instructions
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br r7 ; CHECK-INST: br r7
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; CHECK: encoding: [0x00,0x47]
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dint ; CHECK-INST: dint
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; CHECK: encoding: [0x32,0xc2]
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eint ; CHECK-INST: eint
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; CHECK: encoding: [0x32,0xd2]
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nop ; CHECK-INST: nop
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; CHECK: encoding: [0x03,0x43]
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ret ; CHECK-INST: ret
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; CHECK: encoding: [0x30,0x41]
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;; Emulated data instruction
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clr r7 ; CHECK-INST: clr r7
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; CHECK: encoding: [0x07,0x43]
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clrc ; CHECK-INST: clrc
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; CHECK: encoding: [0x12,0xc3]
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clrn ; CHECK-INST: clrn
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; CHECK: encoding: [0x22,0xc2]
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clrz ; CHECK-INST: clrz
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; CHECK: encoding: [0x22,0xc3]
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pop r7 ; CHECK-INST: pop r7
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; CHECK: encoding: [0x37,0x41]
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setc ; CHECK-INST: setc
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; CHECK: encoding: [0x12,0xd3]
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setn ; CHECK-INST: setn
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; CHECK: encoding: [0x22,0xd2]
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setz ; CHECK-INST: setz
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; CHECK: encoding: [0x22,0xd3]
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tst r7 ; CHECK-INST: tst r7
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; CHECK: encoding: [0x07,0x93]
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