David Green 9b21f6c6fa [ARM] Add MVE addressing to isLegalT2AddressImmediate ... Now with MVE being added, we can add the vector addressing mode costs for it. These are generally imm7 multiplied by the size of the type being loaded / stored. Differential Revision: https://reviews.llvm.org/D62967 llvm-svn: 362873		2019-06-08 10:18:23 +00:00
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Analysis	[ARM] Add MVE addressing to isLegalT2AddressImmediate	2019-06-08 10:18:23 +00:00
Assembler
Bindings
Bitcode
BugPoint
CodeGen	[SystemZ, RegAlloc] Favor 3-address instructions during instruction selection.	2019-06-08 06:19:15 +00:00
DebugInfo	[DebugInfo] Incorrect debug info record generated for loop counter.	2019-06-06 21:19:39 +00:00
Demangle
Examples
ExecutionEngine
Feature
FileCheck	FileCheck [6/12]: Introduce numeric variable definition	2019-06-06 13:21:06 +00:00
Instrumentation	[MSAN] Add unary FNeg visitor to the MemorySanitizer	2019-06-05 22:37:05 +00:00
Integer
JitListener
Linker
LTO
MachineVerifier
MC	[AArch64][AsmParser] error on unexpected SVE predicate type suffix	2019-06-07 08:46:56 +00:00
Object	Attempt to fix nm-archive.test after r362798	2019-06-07 16:06:27 +00:00
ObjectYAML
Other
SafepointIRVerifier
Support
SymbolRewriter
TableGen
ThinLTO/X86
tools	[llvm-objcopy][MachO] Recompute and update offset/size fields in the writer	2019-06-08 01:22:54 +00:00
Transforms	LoopDistribute: Add testcase where SCEV wants to insert a runtime	2019-06-07 23:17:38 +00:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg.py
lit.site.cfg.py.in
TestRunner.sh