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3ee1bf0ca0
This patch adds the instruction definitions and assembly/disassembly tests for the following set of instructions: Vector Extract [byte | half | word | doubleword | quad] with mask Vector Expand [byte | half | word | doubleword | quad] with mask Move to VSR [byte | byte immediate | half | word | doubleword | quad] with mask Vector Count Mask Bits [byte | half | word | doubleword] Differential Revision: https://reviews.llvm.org/D83724 |
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AArch64 | ||
AMDGPU | ||
ARC | ||
ARM | ||
Hexagon | ||
Lanai | ||
Mips | ||
MSP430 | ||
PowerPC | ||
RISCV | ||
Sparc | ||
SystemZ | ||
WebAssembly | ||
X86 | ||
XCore |