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llvm-mirror/test/MC/Disassembler/PowerPC/ppc64-encoding-p9vector.txt
Guozhi Wei 37cf363f24 [PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0 
According to Power ISA V3.0 document, the first source operand of mtvsrdd is constant 0 if r0 is specified. So the corresponding register constraint should be g8rc_nox0.

This bug caused wrong output generated by 401.bzip2 when -mcpu=power9 and fdo are specified.

Differential Revision: https://reviews.llvm.org/D32880

llvm-svn: 302834
2017-05-11 22:17:35 +00:00

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# RUN: llvm-mc --disassemble %s -triple powerpc64le-unknown-unknown -mcpu=pwr9 | FileCheck %s
# CHECK: mtvsrdd 6, 0, 3
0x66 0x1b 0xc0 0x7c
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