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llvm-mirror/test/CodeGen/ARM64/2011-04-21-CPSRBug.ll
Tim Northover 2f13163a84 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

llvm-svn: 205090
2014-03-29 10:18:08 +00:00

27 lines
779 B
LLVM

; RUN: llc < %s -mtriple=arm64-apple-iOS5.0
; CPSR is not allocatable so fast allocatable wouldn't mark them killed.
; rdar://9313272
define hidden void @t() nounwind {
entry:
%cmp = icmp eq i32* null, undef
%frombool = zext i1 %cmp to i8
store i8 %frombool, i8* undef, align 1
%tmp4 = load i8* undef, align 1
%tobool = trunc i8 %tmp4 to i1
br i1 %tobool, label %land.lhs.true, label %if.end
land.lhs.true: ; preds = %entry
unreachable
if.end: ; preds = %entry
br i1 undef, label %land.lhs.true14, label %if.end33
land.lhs.true14: ; preds = %if.end
unreachable
if.end33: ; preds = %if.end
unreachable
}