mirror of
https://github.com/RPCS3/llvm-mirror.git
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2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
215 lines
4.5 KiB
LLVM
215 lines
4.5 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
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define i32 @icmp_eq_imm(i32 %a) nounwind ssp {
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entry:
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; CHECK: icmp_eq_imm
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; CHECK: cmp w0, #31
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; CHECK: csinc w0, wzr, wzr, ne
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%cmp = icmp eq i32 %a, 31
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_eq_neg_imm(i32 %a) nounwind ssp {
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entry:
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; CHECK: icmp_eq_neg_imm
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; CHECK: cmn w0, #7
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; CHECK: csinc w0, wzr, wzr, ne
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%cmp = icmp eq i32 %a, -7
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_eq(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK: icmp_eq
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; CHECK: cmp w0, w1
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; CHECK: csinc w0, wzr, wzr, ne
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%cmp = icmp eq i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_ne(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK: icmp_ne
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; CHECK: cmp w0, w1
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; CHECK: csinc w0, wzr, wzr, eq
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%cmp = icmp ne i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_ugt(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK: icmp_ugt
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; CHECK: cmp w0, w1
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; CHECK: csinc w0, wzr, wzr, ls
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%cmp = icmp ugt i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_uge(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK: icmp_uge
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; CHECK: cmp w0, w1
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; CHECK: csinc w0, wzr, wzr, cc
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%cmp = icmp uge i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_ult(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK: icmp_ult
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; CHECK: cmp w0, w1
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; CHECK: csinc w0, wzr, wzr, cs
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%cmp = icmp ult i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_ule(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK: icmp_ule
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; CHECK: cmp w0, w1
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; CHECK: csinc w0, wzr, wzr, hi
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%cmp = icmp ule i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_sgt(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK: icmp_sgt
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; CHECK: cmp w0, w1
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; CHECK: csinc w0, wzr, wzr, le
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%cmp = icmp sgt i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_sge(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK: icmp_sge
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; CHECK: cmp w0, w1
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; CHECK: csinc w0, wzr, wzr, lt
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%cmp = icmp sge i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_slt(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK: icmp_slt
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; CHECK: cmp w0, w1
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; CHECK: csinc w0, wzr, wzr, ge
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%cmp = icmp slt i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_sle(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK: icmp_sle
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; CHECK: cmp w0, w1
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; CHECK: csinc w0, wzr, wzr, gt
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%cmp = icmp sle i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @icmp_i64(i64 %a, i64 %b) nounwind ssp {
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entry:
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; CHECK: icmp_i64
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; CHECK: cmp x0, x1
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; CHECK: csinc w{{[0-9]+}}, wzr, wzr, gt
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%cmp = icmp sle i64 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define zeroext i1 @icmp_eq_i16(i16 %a, i16 %b) nounwind ssp {
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entry:
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; CHECK: icmp_eq_i16
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; CHECK: sxth w0, w0
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; CHECK: sxth w1, w1
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; CHECK: cmp w0, w1
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; CHECK: csinc w0, wzr, wzr, ne
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%cmp = icmp eq i16 %a, %b
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ret i1 %cmp
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}
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define zeroext i1 @icmp_eq_i8(i8 %a, i8 %b) nounwind ssp {
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entry:
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; CHECK: icmp_eq_i8
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; CHECK: sxtb w0, w0
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; CHECK: sxtb w1, w1
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; CHECK: cmp w0, w1
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; CHECK: csinc w0, wzr, wzr, ne
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%cmp = icmp eq i8 %a, %b
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ret i1 %cmp
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}
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define i32 @icmp_i16_unsigned(i16 %a, i16 %b) nounwind {
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entry:
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; CHECK: icmp_i16_unsigned
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; CHECK: uxth w0, w0
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; CHECK: uxth w1, w1
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; CHECK: cmp w0, w1
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; CHECK: csinc w0, wzr, wzr, cs
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%cmp = icmp ult i16 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define i32 @icmp_i8_signed(i8 %a, i8 %b) nounwind {
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entry:
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; CHECK: @icmp_i8_signed
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; CHECK: sxtb w0, w0
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; CHECK: sxtb w1, w1
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; CHECK: cmp w0, w1
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; CHECK: csinc w0, wzr, wzr, le
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%cmp = icmp sgt i8 %a, %b
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define i32 @icmp_i16_signed_const(i16 %a) nounwind {
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entry:
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; CHECK: icmp_i16_signed_const
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; CHECK: sxth w0, w0
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; CHECK: cmn w0, #233
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; CHECK: csinc w0, wzr, wzr, ge
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; CHECK: and w0, w0, #0x1
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%cmp = icmp slt i16 %a, -233
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define i32 @icmp_i8_signed_const(i8 %a) nounwind {
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entry:
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; CHECK: icmp_i8_signed_const
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; CHECK: sxtb w0, w0
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; CHECK: cmp w0, #124
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; CHECK: csinc w0, wzr, wzr, le
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; CHECK: and w0, w0, #0x1
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%cmp = icmp sgt i8 %a, 124
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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define i32 @icmp_i1_unsigned_const(i1 %a) nounwind {
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entry:
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; CHECK: icmp_i1_unsigned_const
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; CHECK: and w0, w0, #0x1
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; CHECK: cmp w0, #0
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; CHECK: csinc w0, wzr, wzr, cs
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; CHECK: and w0, w0, #0x1
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%cmp = icmp ult i1 %a, 0
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%conv2 = zext i1 %cmp to i32
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ret i32 %conv2
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}
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