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2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
19 lines
616 B
LLVM
19 lines
616 B
LLVM
; RUN: llc -O0 -mtriple=arm64-none-linux-gnu -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s
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; If the .tlsdesccall and blr parts are emitted completely separately (even with
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; glue) then LLVM will separate them quite happily (with a spill at O0, hence
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; the option). This is definitely wrong, so we make sure they are emitted
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; together.
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@general_dynamic_var = external thread_local global i32
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define i32 @test_generaldynamic() {
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; CHECK-LABEL: test_generaldynamic:
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%val = load i32* @general_dynamic_var
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ret i32 %val
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; CHECK: .tlsdesccall general_dynamic_var
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; CHECK-NEXT: blr {{x[0-9]+}}
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}
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