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e25a1a8f41
First patch in a series adding MC layer support for the Arm Scalable
Matrix Extension.
This patch adds the following features:
sme, sme-i64, sme-f64
The sme-i64 and sme-f64 flags are for the optional I16I64 and F64F64
features.
If a target supports I16I64 then the following instructions are
implemented:
* 64-bit integer ADDHA and ADDVA variants (D105570).
* SMOPA, SMOPS, SUMOPA, SUMOPS, UMOPA, UMOPS, USMOPA, and USMOPS
instructions that accumulate 16-bit integer outer products into 64-bit
integer tiles.
If a target supports F64F64 then the FMOPA and FMOPS instructions that
accumulate double-precision floating-point outer products into
double-precision tiles are implemented.
Outer products are implemented in D105571.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06
Reviewed By: CarolineConcatto
Differential Revision: https://reviews.llvm.org/D105569
282 lines
8.5 KiB
C++
282 lines
8.5 KiB
C++
//===-- AArch64TargetParser - Parser for AArch64 features -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise AArch64 hardware features
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// such as FPU/CPU/ARCH and extension names.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/AArch64TargetParser.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Triple.h"
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#include <cctype>
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using namespace llvm;
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static unsigned checkArchVersion(llvm::StringRef Arch) {
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if (Arch.size() >= 2 && Arch[0] == 'v' && std::isdigit(Arch[1]))
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return (Arch[1] - 48);
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return 0;
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}
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unsigned AArch64::getDefaultFPU(StringRef CPU, AArch64::ArchKind AK) {
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if (CPU == "generic")
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return AArch64ARCHNames[static_cast<unsigned>(AK)].DefaultFPU;
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return StringSwitch<unsigned>(CPU)
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#define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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.Case(NAME, ARM::DEFAULT_FPU)
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#include "../../include/llvm/Support/AArch64TargetParser.def"
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.Default(ARM::FK_INVALID);
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}
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uint64_t AArch64::getDefaultExtensions(StringRef CPU, AArch64::ArchKind AK) {
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if (CPU == "generic")
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return AArch64ARCHNames[static_cast<unsigned>(AK)].ArchBaseExtensions;
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return StringSwitch<uint64_t>(CPU)
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#define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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.Case(NAME, AArch64ARCHNames[static_cast<unsigned>(ArchKind::ID)] \
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.ArchBaseExtensions | \
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DEFAULT_EXT)
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#include "../../include/llvm/Support/AArch64TargetParser.def"
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.Default(AArch64::AEK_INVALID);
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}
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AArch64::ArchKind AArch64::getCPUArchKind(StringRef CPU) {
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if (CPU == "generic")
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return ArchKind::ARMV8A;
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return StringSwitch<AArch64::ArchKind>(CPU)
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#define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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.Case(NAME, ArchKind::ID)
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#include "../../include/llvm/Support/AArch64TargetParser.def"
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.Default(ArchKind::INVALID);
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}
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bool AArch64::getExtensionFeatures(uint64_t Extensions,
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std::vector<StringRef> &Features) {
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if (Extensions == AArch64::AEK_INVALID)
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return false;
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if (Extensions & AEK_FP)
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Features.push_back("+fp-armv8");
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if (Extensions & AEK_SIMD)
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Features.push_back("+neon");
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if (Extensions & AEK_CRC)
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Features.push_back("+crc");
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if (Extensions & AEK_CRYPTO)
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Features.push_back("+crypto");
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if (Extensions & AEK_DOTPROD)
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Features.push_back("+dotprod");
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if (Extensions & AEK_FP16FML)
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Features.push_back("+fp16fml");
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if (Extensions & AEK_FP16)
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Features.push_back("+fullfp16");
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if (Extensions & AEK_PROFILE)
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Features.push_back("+spe");
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if (Extensions & AEK_RAS)
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Features.push_back("+ras");
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if (Extensions & AEK_LSE)
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Features.push_back("+lse");
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if (Extensions & AEK_RDM)
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Features.push_back("+rdm");
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if (Extensions & AEK_SVE)
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Features.push_back("+sve");
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if (Extensions & AEK_SVE2)
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Features.push_back("+sve2");
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if (Extensions & AEK_SVE2AES)
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Features.push_back("+sve2-aes");
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if (Extensions & AEK_SVE2SM4)
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Features.push_back("+sve2-sm4");
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if (Extensions & AEK_SVE2SHA3)
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Features.push_back("+sve2-sha3");
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if (Extensions & AEK_SVE2BITPERM)
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Features.push_back("+sve2-bitperm");
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if (Extensions & AEK_RCPC)
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Features.push_back("+rcpc");
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if (Extensions & AEK_BRBE)
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Features.push_back("+brbe");
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if (Extensions & AEK_PAUTH)
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Features.push_back("+pauth");
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if (Extensions & AEK_FLAGM)
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Features.push_back("+flagm");
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if (Extensions & AArch64::AEK_SME)
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Features.push_back("+sme");
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if (Extensions & AArch64::AEK_SMEF64)
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Features.push_back("+sme-f64");
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if (Extensions & AArch64::AEK_SMEI64)
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Features.push_back("+sme-i64");
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return true;
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}
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bool AArch64::getArchFeatures(AArch64::ArchKind AK,
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std::vector<StringRef> &Features) {
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if (AK == ArchKind::ARMV8_1A)
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Features.push_back("+v8.1a");
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if (AK == ArchKind::ARMV8_2A)
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Features.push_back("+v8.2a");
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if (AK == ArchKind::ARMV8_3A)
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Features.push_back("+v8.3a");
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if (AK == ArchKind::ARMV8_4A)
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Features.push_back("+v8.4a");
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if (AK == ArchKind::ARMV8_5A)
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Features.push_back("+v8.5a");
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if (AK == AArch64::ArchKind::ARMV8_6A)
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Features.push_back("+v8.6a");
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if (AK == AArch64::ArchKind::ARMV8_7A)
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Features.push_back("+v8.7a");
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if(AK == AArch64::ArchKind::ARMV8R)
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Features.push_back("+v8r");
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return AK != ArchKind::INVALID;
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}
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StringRef AArch64::getArchName(AArch64::ArchKind AK) {
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return AArch64ARCHNames[static_cast<unsigned>(AK)].getName();
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}
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StringRef AArch64::getCPUAttr(AArch64::ArchKind AK) {
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return AArch64ARCHNames[static_cast<unsigned>(AK)].getCPUAttr();
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}
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StringRef AArch64::getSubArch(AArch64::ArchKind AK) {
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return AArch64ARCHNames[static_cast<unsigned>(AK)].getSubArch();
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}
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unsigned AArch64::getArchAttr(AArch64::ArchKind AK) {
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return AArch64ARCHNames[static_cast<unsigned>(AK)].ArchAttr;
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}
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StringRef AArch64::getArchExtName(unsigned ArchExtKind) {
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for (const auto &AE : AArch64ARCHExtNames)
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if (ArchExtKind == AE.ID)
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return AE.getName();
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return StringRef();
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}
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StringRef AArch64::getArchExtFeature(StringRef ArchExt) {
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if (ArchExt.startswith("no")) {
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StringRef ArchExtBase(ArchExt.substr(2));
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for (const auto &AE : AArch64ARCHExtNames) {
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if (AE.NegFeature && ArchExtBase == AE.getName())
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return StringRef(AE.NegFeature);
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}
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}
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for (const auto &AE : AArch64ARCHExtNames)
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if (AE.Feature && ArchExt == AE.getName())
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return StringRef(AE.Feature);
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return StringRef();
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}
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StringRef AArch64::getDefaultCPU(StringRef Arch) {
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ArchKind AK = parseArch(Arch);
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if (AK == ArchKind::INVALID)
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return StringRef();
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// Look for multiple AKs to find the default for pair AK+Name.
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for (const auto &CPU : AArch64CPUNames)
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if (CPU.ArchID == AK && CPU.Default)
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return CPU.getName();
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// If we can't find a default then target the architecture instead
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return "generic";
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}
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void AArch64::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
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for (const auto &Arch : AArch64CPUNames) {
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if (Arch.ArchID != ArchKind::INVALID)
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Values.push_back(Arch.getName());
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}
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}
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bool AArch64::isX18ReservedByDefault(const Triple &TT) {
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return TT.isAndroid() || TT.isOSDarwin() || TT.isOSFuchsia() ||
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TT.isOSWindows();
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}
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// Allows partial match, ex. "v8a" matches "armv8a".
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AArch64::ArchKind AArch64::parseArch(StringRef Arch) {
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Arch = ARM::getCanonicalArchName(Arch);
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if (checkArchVersion(Arch) < 8)
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return ArchKind::INVALID;
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StringRef Syn = ARM::getArchSynonym(Arch);
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for (const auto &A : AArch64ARCHNames) {
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if (A.getName().endswith(Syn))
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return A.ID;
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}
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return ArchKind::INVALID;
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}
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AArch64::ArchExtKind AArch64::parseArchExt(StringRef ArchExt) {
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for (const auto &A : AArch64ARCHExtNames) {
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if (ArchExt == A.getName())
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return static_cast<ArchExtKind>(A.ID);
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}
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return AArch64::AEK_INVALID;
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}
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AArch64::ArchKind AArch64::parseCPUArch(StringRef CPU) {
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for (const auto &C : AArch64CPUNames) {
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if (CPU == C.getName())
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return C.ArchID;
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}
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return ArchKind::INVALID;
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}
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// Parse a branch protection specification, which has the form
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// standard | none | [bti,pac-ret[+b-key,+leaf]*]
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// Returns true on success, with individual elements of the specification
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// returned in `PBP`. Returns false in error, with `Err` containing
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// an erroneous part of the spec.
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bool AArch64::parseBranchProtection(StringRef Spec, ParsedBranchProtection &PBP,
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StringRef &Err) {
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PBP = {"none", "a_key", false};
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if (Spec == "none")
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return true; // defaults are ok
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if (Spec == "standard") {
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PBP.Scope = "non-leaf";
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PBP.BranchTargetEnforcement = true;
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return true;
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}
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SmallVector<StringRef, 4> Opts;
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Spec.split(Opts, "+");
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for (int I = 0, E = Opts.size(); I != E; ++I) {
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StringRef Opt = Opts[I].trim();
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if (Opt == "bti") {
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PBP.BranchTargetEnforcement = true;
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continue;
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}
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if (Opt == "pac-ret") {
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PBP.Scope = "non-leaf";
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for (; I + 1 != E; ++I) {
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StringRef PACOpt = Opts[I + 1].trim();
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if (PACOpt == "leaf")
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PBP.Scope = "all";
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else if (PACOpt == "b-key")
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PBP.Key = "b_key";
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else
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break;
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}
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continue;
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}
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if (Opt == "")
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Err = "<empty>";
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else
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Err = Opt;
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return false;
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}
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return true;
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}
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