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114 lines
3.7 KiB
LLVM
114 lines
3.7 KiB
LLVM
; RUN: llc -march=hexagon -debug-only=isel < %s 2>&1 | FileCheck %s
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; REQUIRES: asserts
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; This test validates that ISel picks the correct equivalent of below mentioned intrinsics
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; For S2_asr_i_r_rnd_goodsyntax:
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; if (#u5 == 0) Assembler mapped to: Rd = Rs
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; else Rd = asr(Rs,#u5-1):rnd
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; For S2_asr_i_p_rnd_goodsyntax:
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; if (#u6 == 0) Assembler mapped to: Rdd = combine(Rss.H32,Rss.L32)
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; else Rdd = asr(Rss,#u6-1):rnd
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; For S5_vasrhrnd_goodsyntax:
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; if (#u4 == 0) Assembler mapped to: Rdd = combine(Rss.H32,Rss.L32)
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; else Rdd = vasrh(Rss,#u4-1):raw
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; For S5_asrhub_rnd_sat_goodsyntax:
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; if (#u4 == 0) Assembler mapped to: Rd = vsathub(Rss)
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; else Rd = vasrhub(Rss,#u4-1):raw
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target triple = "hexagon-unknown--elf"
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; CHECK-LABEL: f0
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; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S2.asr.i.r.rnd.goodsyntax
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; CHECK: Morphed node{{.*}}A2_tfr
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define i32 @f0(i32 %a0, i32 %a1) local_unnamed_addr #0 {
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b0:
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%v0 = tail call i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32 %a0, i32 0)
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%v1 = add i32 %v0, %a1
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ret i32 %v1
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}
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declare i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32, i32) #1
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; CHECK-LABEL: f1
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; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S2.asr.i.r.rnd.goodsyntax
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; CHECK: Morphed node{{.*}}S2_asr_i_r_rnd
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define i32 @f1(i32 %a0, i32 %a1) local_unnamed_addr #0 {
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b0:
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%v0 = tail call i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32 %a0, i32 9)
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%v1 = add i32 %v0, %a1
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ret i32 %v1
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}
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; CHECK-LABEL: f2
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; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S2.asr.i.p.rnd.goodsyntax
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; CHECK: Morphed node{{.*}}A2_combinew
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define i64 @f2(i64 %a0, i32 %a1) local_unnamed_addr #0 {
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b0:
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%v0 = zext i32 %a1 to i64
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%v1 = tail call i64 @llvm.hexagon.S2.asr.i.p.rnd.goodsyntax(i64 %a0, i32 0)
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%v2 = add nsw i64 %v1, %v0
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ret i64 %v2
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}
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declare i64 @llvm.hexagon.S2.asr.i.p.rnd.goodsyntax(i64, i32) #1
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; CHECK-LABEL: f3
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; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S2.asr.i.p.rnd.goodsyntax
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; CHECK: Morphed node{{.*}}S2_asr_i_p_rnd
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define i64 @f3(i64 %a0, i32 %a1) local_unnamed_addr #0 {
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b0:
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%v0 = zext i32 %a1 to i64
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%v1 = tail call i64 @llvm.hexagon.S2.asr.i.p.rnd.goodsyntax(i64 %a0, i32 9)
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%v2 = add nsw i64 %v1, %v0
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ret i64 %v2
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}
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; CHECK-LABEL: f4
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; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax
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; CHECK: Morphed node{{.*}}S2_vsathub
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define i32 @f4(i64 %a0, i32 %a1) local_unnamed_addr #0 {
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b0:
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%v0 = tail call i32 @llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax(i64 %a0, i32 0)
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%v1 = add i32 %v0, %a1
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ret i32 %v1
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}
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declare i32 @llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax(i64, i32) #1
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; CHECK-LABEL: f5
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; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax
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; CHECK: Morphed node{{.*}}S5_asrhub_rnd_sat
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define i32 @f5(i64 %a0, i32 %a1) local_unnamed_addr #0 {
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b0:
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%v0 = tail call i32 @llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax(i64 %a0, i32 9)
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%v1 = add i32 %v0, %a1
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ret i32 %v1
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}
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; CHECK-LABEL: f6
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; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S5.vasrhrnd.goodsyntax
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; CHECK: Morphed node{{.*}}A2_combinew
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define i64 @f6(i64 %a0, i32 %a1) local_unnamed_addr #0 {
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b0:
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%v0 = zext i32 %a1 to i64
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%v1 = tail call i64 @llvm.hexagon.S5.vasrhrnd.goodsyntax(i64 %a0, i32 0)
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%v2 = add nsw i64 %v1, %v0
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ret i64 %v2
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}
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declare i64 @llvm.hexagon.S5.vasrhrnd.goodsyntax(i64, i32) #1
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; CHECK-LABEL: f7
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; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S5.vasrhrnd.goodsyntax
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; CHECK: Morphed node{{.*}}S5_vasrhrnd
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define i64 @f7(i64 %a0, i32 %a1) local_unnamed_addr #0 {
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b0:
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%v0 = zext i32 %a1 to i64
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%v1 = tail call i64 @llvm.hexagon.S5.vasrhrnd.goodsyntax(i64 %a0, i32 9)
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%v2 = add nsw i64 %v1, %v0
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ret i64 %v2
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}
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" }
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attributes #1 = { nounwind readnone }
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