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20 lines
456 B
LLVM
20 lines
456 B
LLVM
; RUN: llc -march=hexagon < %s
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; Check that the mis-aligned load doesn't cause compiler to assert.
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@g0 = common global i32 0, align 4
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declare i32 @f0(i64) #0
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define i32 @f1() #0 {
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b0:
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%v0 = alloca i32, align 4
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%v1 = load i32, i32* @g0, align 4
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store i32 %v1, i32* %v0, align 4
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%v2 = bitcast i32* %v0 to i64*
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%v3 = load i64, i64* %v2, align 8
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%v4 = call i32 @f0(i64 %v3)
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ret i32 %v4
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv5" }
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