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shift. 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> llvm-svn: 126723
12 lines
420 B
LLVM
12 lines
420 B
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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; <rdar://problem/9055897>
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define <4 x i16> @t1(<4 x i32> %a) nounwind {
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entry:
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; CHECK: vqrshrn.s32 d{{[0-9]+}}, q{{[0-9]*}}, #13
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%x = tail call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %a, <4 x i32> <i32 -13, i32 -13, i32 -13, i32 -13>)
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ret <4 x i16> %x
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}
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declare <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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