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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
103 lines
3.3 KiB
C++
103 lines
3.3 KiB
C++
//===-- RegisterAliasingTest.cpp --------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "RegisterAliasing.h"
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#include <cassert>
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#include <memory>
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#include "X86InstrInfo.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "gmock/gmock.h"
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#include "gtest/gtest.h"
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namespace llvm {
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namespace exegesis {
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namespace {
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class RegisterAliasingTest : public ::testing::Test {
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protected:
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RegisterAliasingTest() {
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const std::string TT = "x86_64-unknown-linux";
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std::string error;
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const llvm::Target *const TheTarget =
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llvm::TargetRegistry::lookupTarget(TT, error);
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if (!TheTarget) {
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llvm::errs() << error << "\n";
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return;
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}
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MCRegInfo.reset(TheTarget->createMCRegInfo(TT));
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}
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static void SetUpTestCase() {
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LLVMInitializeX86TargetInfo();
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LLVMInitializeX86Target();
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LLVMInitializeX86TargetMC();
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}
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const llvm::MCRegisterInfo &getMCRegInfo() {
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assert(MCRegInfo);
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return *MCRegInfo;
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}
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private:
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std::unique_ptr<const llvm::MCRegisterInfo> MCRegInfo;
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};
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TEST_F(RegisterAliasingTest, TrackSimpleRegister) {
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const auto &RegInfo = getMCRegInfo();
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const RegisterAliasingTracker tracker(RegInfo, llvm::X86::EAX);
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std::set<llvm::MCPhysReg> ActualAliasedRegisters;
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for (unsigned I : tracker.aliasedBits().set_bits())
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ActualAliasedRegisters.insert(static_cast<llvm::MCPhysReg>(I));
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const std::set<llvm::MCPhysReg> ExpectedAliasedRegisters = {
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llvm::X86::AL, llvm::X86::AH, llvm::X86::AX,
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llvm::X86::EAX, llvm::X86::HAX, llvm::X86::RAX};
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ASSERT_THAT(ActualAliasedRegisters, ExpectedAliasedRegisters);
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for (llvm::MCPhysReg aliased : ExpectedAliasedRegisters) {
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ASSERT_THAT(tracker.getOrigin(aliased), llvm::X86::EAX);
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}
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}
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TEST_F(RegisterAliasingTest, TrackRegisterClass) {
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// The alias bits for GR8_ABCD_LRegClassID are the union of the alias bits for
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// AL, BL, CL and DL.
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const auto &RegInfo = getMCRegInfo();
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const llvm::BitVector NoReservedReg(RegInfo.getNumRegs());
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const RegisterAliasingTracker RegClassTracker(
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RegInfo, NoReservedReg,
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RegInfo.getRegClass(llvm::X86::GR8_ABCD_LRegClassID));
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llvm::BitVector sum(RegInfo.getNumRegs());
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sum |= RegisterAliasingTracker(RegInfo, llvm::X86::AL).aliasedBits();
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sum |= RegisterAliasingTracker(RegInfo, llvm::X86::BL).aliasedBits();
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sum |= RegisterAliasingTracker(RegInfo, llvm::X86::CL).aliasedBits();
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sum |= RegisterAliasingTracker(RegInfo, llvm::X86::DL).aliasedBits();
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ASSERT_THAT(RegClassTracker.aliasedBits(), sum);
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}
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TEST_F(RegisterAliasingTest, TrackRegisterClassCache) {
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// Fetching twice the same tracker yields the same pointers.
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const auto &RegInfo = getMCRegInfo();
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const llvm::BitVector NoReservedReg(RegInfo.getNumRegs());
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RegisterAliasingTrackerCache Cache(RegInfo, NoReservedReg);
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ASSERT_THAT(&Cache.getRegister(llvm::X86::AX),
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&Cache.getRegister(llvm::X86::AX));
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ASSERT_THAT(&Cache.getRegisterClass(llvm::X86::GR8_ABCD_LRegClassID),
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&Cache.getRegisterClass(llvm::X86::GR8_ABCD_LRegClassID));
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}
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} // namespace
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} // namespace exegesis
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} // namespace llvm
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