Evan Cheng 9c3f6f486e - Add a hook for target to determine whether an instruction def is ... "long latency" enough to hoist even if it may increase spilling. Reloading a value from spill slot is often cheaper than performing an expensive computation in the loop. For X86, that means machine LICM will hoist SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON instructions. - Enable register pressure aware machine LICM by default. llvm-svn: 116781		2010-10-19 00:55:07 +00:00
..
Alpha
ARM	- Add a hook for target to determine whether an instruction def is	2010-10-19 00:55:07 +00:00
Blackfin
CBackend
CellSPU	Improve lowering of sext to i128 on SPU.	2010-10-18 09:34:19 +00:00
CPP
Generic
MBlaze
Mips	Enable machine sinking critical edge splitting. e.g.	2010-09-20 22:52:00 +00:00
MSP430	CombinerAA is now reordering these stores.	2010-09-20 20:56:29 +00:00
PowerPC	PowerPC varargs functions store live-in registers on the stack. Make sure we use	2010-10-11 20:43:09 +00:00
PTX	Add test case for PTX ret instruction	2010-09-25 07:49:54 +00:00
SPARC
SystemZ	Correct bogus module triple specifications.	2010-08-30 10:48:29 +00:00
Thumb	Try again to disable critical edge splitting in CodeGenPrepare.	2010-09-30 20:51:52 +00:00
Thumb2	- Add a hook for target to determine whether an instruction def is	2010-10-19 00:55:07 +00:00
X86	- Add a hook for target to determine whether an instruction def is	2010-10-19 00:55:07 +00:00
XCore	Enable machine sinking critical edge splitting. e.g.	2010-09-20 22:52:00 +00:00
thumb2-mul.ll	Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes	2010-09-21 22:51:46 +00:00