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2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
35 lines
814 B
LLVM
35 lines
814 B
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
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define <2 x i32> @c1(<2 x float> %a) nounwind readnone ssp {
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; CHECK: c1
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; CHECK: fcvtzs.2s v0, v0
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; CHECK: ret
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%vcvt.i = fptosi <2 x float> %a to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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define <2 x i32> @c2(<2 x float> %a) nounwind readnone ssp {
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; CHECK: c2
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; CHECK: fcvtzu.2s v0, v0
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; CHECK: ret
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%vcvt.i = fptoui <2 x float> %a to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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define <4 x i32> @c3(<4 x float> %a) nounwind readnone ssp {
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; CHECK: c3
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; CHECK: fcvtzs.4s v0, v0
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; CHECK: ret
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%vcvt.i = fptosi <4 x float> %a to <4 x i32>
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ret <4 x i32> %vcvt.i
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}
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define <4 x i32> @c4(<4 x float> %a) nounwind readnone ssp {
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; CHECK: c4
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; CHECK: fcvtzu.4s v0, v0
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; CHECK: ret
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%vcvt.i = fptoui <4 x float> %a to <4 x i32>
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ret <4 x i32> %vcvt.i
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}
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