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llvm-mirror/test/CodeGen/Hexagon/vect/vect-no-tfrs.ll
Krzysztof Parzyszek 9cc7bfdeec [Hexagon] Add support for vector instructions
llvm-svn: 232728
2015-03-19 16:33:08 +00:00

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196 B
LLVM

; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK-NOT: r1:0 = combine(r1, r0)
define <4 x i8> @t_i4x8(<4 x i8> %a, <4 x i8> %b) nounwind {
entry:
%0 = mul <4 x i8> %a, %b
ret <4 x i8> %0
}