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https://github.com/RPCS3/llvm-mirror.git
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251919f579
LLVM normally prefers to minimize the number of bits set in an AND immediate, but that doesn't always match the available ARM instructions. In Thumb1 mode, prefer uxtb or uxth where possible; otherwise, prefer a two-instruction sequence movs+ands or movs+bics. Some potential improvements outlined in ARMTargetLowering::targetShrinkDemandedConstant, but seems to work pretty well already. The ARMISelDAGToDAG fix ensures we don't generate an invalid UBFX instruction due to a larger-than-expected mask. (It's orthogonal, in some sense, but as far as I can tell it's either impossible or nearly impossible to reproduce the bug without this change.) According to my testing, this seems to consistently improve codesize by a small amount by forming bic more often for ISD::AND with an immediate. Differential Revision: https://reviews.llvm.org/D50030 llvm-svn: 339472
326 lines
8.6 KiB
LLVM
326 lines
8.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-eabi-unknown-unknown | FileCheck %s
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; Select of constants: control flow / conditional moves can always be replaced by logic+math (but may not be worth it?).
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; Test the zeroext/signext variants of each pattern to see if that makes a difference.
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; select Cond, 0, 1 --> zext (!Cond)
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define i32 @select_0_or_1(i1 %cond) {
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; CHECK-LABEL: select_0_or_1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #1
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; CHECK-NEXT: bic r0, r1, r0
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 0, i32 1
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ret i32 %sel
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}
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define i32 @select_0_or_1_zeroext(i1 zeroext %cond) {
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; CHECK-LABEL: select_0_or_1_zeroext:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: eor r0, r0, #1
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 0, i32 1
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ret i32 %sel
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}
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define i32 @select_0_or_1_signext(i1 signext %cond) {
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; CHECK-LABEL: select_0_or_1_signext:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #1
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; CHECK-NEXT: bic r0, r1, r0
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 0, i32 1
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ret i32 %sel
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}
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; select Cond, 1, 0 --> zext (Cond)
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define i32 @select_1_or_0(i1 %cond) {
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; CHECK-LABEL: select_1_or_0:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: and r0, r0, #1
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 1, i32 0
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ret i32 %sel
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}
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define i32 @select_1_or_0_zeroext(i1 zeroext %cond) {
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; CHECK-LABEL: select_1_or_0_zeroext:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 1, i32 0
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ret i32 %sel
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}
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define i32 @select_1_or_0_signext(i1 signext %cond) {
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; CHECK-LABEL: select_1_or_0_signext:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: and r0, r0, #1
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 1, i32 0
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ret i32 %sel
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}
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; select Cond, 0, -1 --> sext (!Cond)
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define i32 @select_0_or_neg1(i1 %cond) {
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; CHECK-LABEL: select_0_or_neg1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #1
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; CHECK-NEXT: bic r0, r1, r0
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; CHECK-NEXT: rsb r0, r0, #0
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 0, i32 -1
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ret i32 %sel
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}
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define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) {
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; CHECK-LABEL: select_0_or_neg1_zeroext:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: eor r0, r0, #1
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; CHECK-NEXT: rsb r0, r0, #0
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 0, i32 -1
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ret i32 %sel
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}
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define i32 @select_0_or_neg1_signext(i1 signext %cond) {
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; CHECK-LABEL: select_0_or_neg1_signext:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mvn r0, r0
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 0, i32 -1
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ret i32 %sel
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}
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define i32 @select_0_or_neg1_alt(i1 %cond) {
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; CHECK-LABEL: select_0_or_neg1_alt:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: and r0, r0, #1
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; CHECK-NEXT: sub r0, r0, #1
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; CHECK-NEXT: mov pc, lr
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%z = zext i1 %cond to i32
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%add = add i32 %z, -1
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ret i32 %add
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}
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define i32 @select_0_or_neg1_alt_zeroext(i1 zeroext %cond) {
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; CHECK-LABEL: select_0_or_neg1_alt_zeroext:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: sub r0, r0, #1
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; CHECK-NEXT: mov pc, lr
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%z = zext i1 %cond to i32
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%add = add i32 %z, -1
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ret i32 %add
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}
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define i32 @select_0_or_neg1_alt_signext(i1 signext %cond) {
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; CHECK-LABEL: select_0_or_neg1_alt_signext:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mvn r0, r0
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; CHECK-NEXT: mov pc, lr
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%z = zext i1 %cond to i32
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%add = add i32 %z, -1
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ret i32 %add
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}
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; select Cond, -1, 0 --> sext (Cond)
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define i32 @select_neg1_or_0(i1 %cond) {
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; CHECK-LABEL: select_neg1_or_0:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: and r0, r0, #1
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; CHECK-NEXT: rsb r0, r0, #0
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 -1, i32 0
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ret i32 %sel
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}
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define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) {
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; CHECK-LABEL: select_neg1_or_0_zeroext:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: rsb r0, r0, #0
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 -1, i32 0
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ret i32 %sel
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}
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define i32 @select_neg1_or_0_signext(i1 signext %cond) {
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; CHECK-LABEL: select_neg1_or_0_signext:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 -1, i32 0
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ret i32 %sel
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}
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; select Cond, C+1, C --> add (zext Cond), C
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define i32 @select_Cplus1_C(i1 %cond) {
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; CHECK-LABEL: select_Cplus1_C:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #41
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; CHECK-NEXT: tst r0, #1
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; CHECK-NEXT: movne r1, #42
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 42, i32 41
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ret i32 %sel
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}
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define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) {
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; CHECK-LABEL: select_Cplus1_C_zeroext:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #41
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: movne r1, #42
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 42, i32 41
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ret i32 %sel
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}
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define i32 @select_Cplus1_C_signext(i1 signext %cond) {
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; CHECK-LABEL: select_Cplus1_C_signext:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #41
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; CHECK-NEXT: tst r0, #1
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; CHECK-NEXT: movne r1, #42
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 42, i32 41
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ret i32 %sel
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}
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; select Cond, C, C+1 --> add (sext Cond), C
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define i32 @select_C_Cplus1(i1 %cond) {
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; CHECK-LABEL: select_C_Cplus1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #42
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; CHECK-NEXT: tst r0, #1
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; CHECK-NEXT: movne r1, #41
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 41, i32 42
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ret i32 %sel
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}
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define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) {
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; CHECK-LABEL: select_C_Cplus1_zeroext:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #42
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: movne r1, #41
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 41, i32 42
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ret i32 %sel
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}
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define i32 @select_C_Cplus1_signext(i1 signext %cond) {
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; CHECK-LABEL: select_C_Cplus1_signext:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #42
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; CHECK-NEXT: tst r0, #1
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; CHECK-NEXT: movne r1, #41
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 41, i32 42
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ret i32 %sel
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}
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; In general, select of 2 constants could be:
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; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2 --> add (and (sext Cond), C1-C2), C2
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define i32 @select_C1_C2(i1 %cond) {
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; CHECK-LABEL: select_C1_C2:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #165
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; CHECK-NEXT: tst r0, #1
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; CHECK-NEXT: orr r1, r1, #256
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; CHECK-NEXT: moveq r1, #42
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 421, i32 42
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ret i32 %sel
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}
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define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {
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; CHECK-LABEL: select_C1_C2_zeroext:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #165
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: orr r1, r1, #256
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; CHECK-NEXT: moveq r1, #42
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 421, i32 42
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ret i32 %sel
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}
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define i32 @select_C1_C2_signext(i1 signext %cond) {
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; CHECK-LABEL: select_C1_C2_signext:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #165
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; CHECK-NEXT: tst r0, #1
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; CHECK-NEXT: orr r1, r1, #256
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; CHECK-NEXT: moveq r1, #42
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i32 421, i32 42
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ret i32 %sel
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}
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; 4295032833 = 0x100010001.
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; This becomes an opaque constant via ConstantHoisting, so we don't fold it into the select.
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define i64 @opaque_constant1(i1 %cond, i64 %x) {
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; CHECK-LABEL: opaque_constant1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: mov lr, #1
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; CHECK-NEXT: ands r12, r0, #1
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; CHECK-NEXT: mov r0, #23
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; CHECK-NEXT: orr lr, lr, #65536
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; CHECK-NEXT: mvnne r0, #3
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; CHECK-NEXT: and r4, r0, lr
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; CHECK-NEXT: movne r12, #1
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; CHECK-NEXT: subs r0, r4, #1
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; CHECK-NEXT: eor r2, r2, lr
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; CHECK-NEXT: eor r3, r3, #1
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; CHECK-NEXT: sbc r1, r12, #0
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; CHECK-NEXT: orrs r2, r2, r3
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; CHECK-NEXT: movne r0, r4
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; CHECK-NEXT: movne r1, r12
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; CHECK-NEXT: pop {r4, lr}
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i64 -4, i64 23
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%bo = and i64 %sel, 4295032833 ; 0x100010001
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%cmp = icmp eq i64 %x, 4295032833
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%sext = sext i1 %cmp to i64
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%add = add i64 %bo, %sext
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ret i64 %add
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}
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; 65537 == 0x10001.
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; This becomes an opaque constant via ConstantHoisting, so we don't fold it into the select.
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define i64 @opaque_constant2(i1 %cond, i64 %x) {
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; CHECK-LABEL: opaque_constant2:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r1, #1
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; CHECK-NEXT: tst r0, #1
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; CHECK-NEXT: orr r1, r1, #65536
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; CHECK-NEXT: moveq r1, #23
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; CHECK-NEXT: bic r0, r1, #22
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; CHECK-NEXT: mov r1, #0
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; CHECK-NEXT: mov pc, lr
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%sel = select i1 %cond, i64 65537, i64 23
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%bo = and i64 %sel, 65537
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ret i64 %bo
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}
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