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f1715d1306
When matching an interleaved load to an ldN pattern, the interleaved access pass checks that all users of the load are shuffles. If the load is used by an instruction other than a shuffle, the pass gives up and an ldN is not generated. This patch considers users of the load that are extractelement instructions. It attempts to modify the extracts to use one of the available shuffles rather than the load. After the transformation, the load is only used by shuffles and will then be matched with an ldN pattern. Differential Revision: http://reviews.llvm.org/D20250 llvm-svn: 270142
319 lines
14 KiB
LLVM
319 lines
14 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon -lower-interleaved-accesses=true < %s | FileCheck %s -check-prefix=NEON
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; RUN: llc -mtriple=arm-eabi -mattr=-neon -lower-interleaved-accesses=true < %s | FileCheck %s -check-prefix=NONEON
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; NEON-LABEL: load_factor2:
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; NEON: vld2.8 {d16, d17}, [r0]
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; NONEON-LABEL: load_factor2:
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; NONEON-NOT: vld2
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define <8 x i8> @load_factor2(<16 x i8>* %ptr) {
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%wide.vec = load <16 x i8>, <16 x i8>* %ptr, align 4
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%strided.v0 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%strided.v1 = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%add = add nsw <8 x i8> %strided.v0, %strided.v1
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ret <8 x i8> %add
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}
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; NEON-LABEL: load_factor3:
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; NEON: vld3.32 {d16, d17, d18}, [r0]
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; NONEON-LABEL: load_factor3:
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; NONEON-NOT: vld3
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define <2 x i32> @load_factor3(i32* %ptr) {
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%base = bitcast i32* %ptr to <6 x i32>*
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%wide.vec = load <6 x i32>, <6 x i32>* %base, align 4
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%strided.v2 = shufflevector <6 x i32> %wide.vec, <6 x i32> undef, <2 x i32> <i32 2, i32 5>
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%strided.v1 = shufflevector <6 x i32> %wide.vec, <6 x i32> undef, <2 x i32> <i32 1, i32 4>
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%add = add nsw <2 x i32> %strided.v2, %strided.v1
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ret <2 x i32> %add
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}
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; NEON-LABEL: load_factor4:
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; NEON: vld4.32 {d16, d18, d20, d22}, [r0]!
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; NEON: vld4.32 {d17, d19, d21, d23}, [r0]
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; NONEON-LABEL: load_factor4:
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; NONEON-NOT: vld4
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define <4 x i32> @load_factor4(i32* %ptr) {
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%base = bitcast i32* %ptr to <16 x i32>*
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%wide.vec = load <16 x i32>, <16 x i32>* %base, align 4
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%strided.v0 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
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%strided.v2 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
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%add = add nsw <4 x i32> %strided.v0, %strided.v2
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ret <4 x i32> %add
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}
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; NEON-LABEL: store_factor2:
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; NEON: vst2.8 {d16, d17}, [r0]
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; NONEON-LABEL: store_factor2:
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; NONEON-NOT: vst2
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define void @store_factor2(<16 x i8>* %ptr, <8 x i8> %v0, <8 x i8> %v1) {
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%interleaved.vec = shufflevector <8 x i8> %v0, <8 x i8> %v1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
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store <16 x i8> %interleaved.vec, <16 x i8>* %ptr, align 4
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ret void
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}
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; NEON-LABEL: store_factor3:
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; NEON: vst3.32 {d16, d18, d20}, [r0]!
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; NEON: vst3.32 {d17, d19, d21}, [r0]
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; NONEON-LABEL: store_factor3:
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; NONEON-NOT: vst3.32
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define void @store_factor3(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
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%base = bitcast i32* %ptr to <12 x i32>*
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%v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%v2_u = shufflevector <4 x i32> %v2, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
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%interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_u, <12 x i32> <i32 0, i32 4, i32 8, i32 1, i32 5, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
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store <12 x i32> %interleaved.vec, <12 x i32>* %base, align 4
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ret void
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}
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; NEON-LABEL: store_factor4:
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; NEON: vst4.32 {d16, d18, d20, d22}, [r0]!
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; NEON: vst4.32 {d17, d19, d21, d23}, [r0]
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; NONEON-LABEL: store_factor4:
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; NONEON-NOT: vst4
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define void @store_factor4(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
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%base = bitcast i32* %ptr to <16 x i32>*
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%v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%v2_v3 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_v3, <16 x i32> <i32 0, i32 4, i32 8, i32 12, i32 1, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
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store <16 x i32> %interleaved.vec, <16 x i32>* %base, align 4
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ret void
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}
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; The following cases test that interleaved access of pointer vectors can be
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; matched to ldN/stN instruction.
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; NEON-LABEL: load_ptrvec_factor2:
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; NEON: vld2.32 {d16, d17}, [r0]
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; NONEON-LABEL: load_ptrvec_factor2:
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; NONEON-NOT: vld2
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define <2 x i32*> @load_ptrvec_factor2(i32** %ptr) {
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%base = bitcast i32** %ptr to <4 x i32*>*
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%wide.vec = load <4 x i32*>, <4 x i32*>* %base, align 4
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%strided.v0 = shufflevector <4 x i32*> %wide.vec, <4 x i32*> undef, <2 x i32> <i32 0, i32 2>
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ret <2 x i32*> %strided.v0
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}
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; NEON-LABEL: load_ptrvec_factor3:
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; NEON: vld3.32 {d16, d17, d18}, [r0]
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; NONEON-LABEL: load_ptrvec_factor3:
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; NONEON-NOT: vld3
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define void @load_ptrvec_factor3(i32** %ptr, <2 x i32*>* %ptr1, <2 x i32*>* %ptr2) {
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%base = bitcast i32** %ptr to <6 x i32*>*
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%wide.vec = load <6 x i32*>, <6 x i32*>* %base, align 4
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%strided.v2 = shufflevector <6 x i32*> %wide.vec, <6 x i32*> undef, <2 x i32> <i32 2, i32 5>
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store <2 x i32*> %strided.v2, <2 x i32*>* %ptr1
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%strided.v1 = shufflevector <6 x i32*> %wide.vec, <6 x i32*> undef, <2 x i32> <i32 1, i32 4>
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store <2 x i32*> %strided.v1, <2 x i32*>* %ptr2
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ret void
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}
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; NEON-LABEL: load_ptrvec_factor4:
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; NEON: vld4.32 {d16, d17, d18, d19}, [r0]
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; NONEON-LABEL: load_ptrvec_factor4:
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; NONEON-NOT: vld4
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define void @load_ptrvec_factor4(i32** %ptr, <2 x i32*>* %ptr1, <2 x i32*>* %ptr2) {
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%base = bitcast i32** %ptr to <8 x i32*>*
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%wide.vec = load <8 x i32*>, <8 x i32*>* %base, align 4
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%strided.v1 = shufflevector <8 x i32*> %wide.vec, <8 x i32*> undef, <2 x i32> <i32 1, i32 5>
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%strided.v3 = shufflevector <8 x i32*> %wide.vec, <8 x i32*> undef, <2 x i32> <i32 3, i32 7>
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store <2 x i32*> %strided.v1, <2 x i32*>* %ptr1
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store <2 x i32*> %strided.v3, <2 x i32*>* %ptr2
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ret void
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}
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; NEON-LABEL: store_ptrvec_factor2:
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; NEON: vst2.32 {d16, d17}, [r0]
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; NONEON-LABEL: store_ptrvec_factor2:
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; NONEON-NOT: vst2
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define void @store_ptrvec_factor2(i32** %ptr, <2 x i32*> %v0, <2 x i32*> %v1) {
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%base = bitcast i32** %ptr to <4 x i32*>*
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%interleaved.vec = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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store <4 x i32*> %interleaved.vec, <4 x i32*>* %base, align 4
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ret void
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}
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; NEON-LABEL: store_ptrvec_factor3:
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; NEON: vst3.32 {d16, d17, d18}, [r0]
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; NONEON-LABEL: store_ptrvec_factor3:
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; NONEON-NOT: vst3
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define void @store_ptrvec_factor3(i32** %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2) {
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%base = bitcast i32** %ptr to <6 x i32*>*
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%v0_v1 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%v2_u = shufflevector <2 x i32*> %v2, <2 x i32*> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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%interleaved.vec = shufflevector <4 x i32*> %v0_v1, <4 x i32*> %v2_u, <6 x i32> <i32 0, i32 2, i32 4, i32 1, i32 3, i32 5>
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store <6 x i32*> %interleaved.vec, <6 x i32*>* %base, align 4
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ret void
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}
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; NEON-LABEL: store_ptrvec_factor4:
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; NEON: vst4.32 {d16, d17, d18, d19}, [r0]
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; NONEON-LABEL: store_ptrvec_factor4:
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; NONEON-NOT: vst4
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define void @store_ptrvec_factor4(i32* %ptr, <2 x i32*> %v0, <2 x i32*> %v1, <2 x i32*> %v2, <2 x i32*> %v3) {
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%base = bitcast i32* %ptr to <8 x i32*>*
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%v0_v1 = shufflevector <2 x i32*> %v0, <2 x i32*> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%v2_v3 = shufflevector <2 x i32*> %v2, <2 x i32*> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%interleaved.vec = shufflevector <4 x i32*> %v0_v1, <4 x i32*> %v2_v3, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
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store <8 x i32*> %interleaved.vec, <8 x i32*>* %base, align 4
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ret void
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}
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; Following cases check that shuffle maskes with undef indices can be matched
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; into ldN/stN instruction.
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; NEON-LABEL: load_undef_mask_factor2:
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; NEON: vld2.32 {d16, d17, d18, d19}, [r0]
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; NONEON-LABEL: load_undef_mask_factor2:
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; NONEON-NOT: vld2
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define <4 x i32> @load_undef_mask_factor2(i32* %ptr) {
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%base = bitcast i32* %ptr to <8 x i32>*
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%wide.vec = load <8 x i32>, <8 x i32>* %base, align 4
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%strided.v0 = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 6>
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%strided.v1 = shufflevector <8 x i32> %wide.vec, <8 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 7>
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%add = add nsw <4 x i32> %strided.v0, %strided.v1
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ret <4 x i32> %add
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}
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; NEON-LABEL: load_undef_mask_factor3:
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; NEON: vld3.32 {d16, d18, d20}, [r0]!
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; NEON: vld3.32 {d17, d19, d21}, [r0]
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; NONEON-LABEL: load_undef_mask_factor3:
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; NONEON-NOT: vld3
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define <4 x i32> @load_undef_mask_factor3(i32* %ptr) {
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%base = bitcast i32* %ptr to <12 x i32>*
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%wide.vec = load <12 x i32>, <12 x i32>* %base, align 4
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%strided.v2 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef>
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%strided.v1 = shufflevector <12 x i32> %wide.vec, <12 x i32> undef, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
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%add = add nsw <4 x i32> %strided.v2, %strided.v1
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ret <4 x i32> %add
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}
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; NEON-LABEL: load_undef_mask_factor4:
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; NEON: vld4.32 {d16, d18, d20, d22}, [r0]!
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; NEON: vld4.32 {d17, d19, d21, d23}, [r0]
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; NONEON-LABEL: load_undef_mask_factor4:
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; NONEON-NOT: vld4
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define <4 x i32> @load_undef_mask_factor4(i32* %ptr) {
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%base = bitcast i32* %ptr to <16 x i32>*
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%wide.vec = load <16 x i32>, <16 x i32>* %base, align 4
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%strided.v0 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 undef, i32 undef>
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%strided.v2 = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 2, i32 6, i32 undef, i32 undef>
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%add = add nsw <4 x i32> %strided.v0, %strided.v2
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ret <4 x i32> %add
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}
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; NEON-LABEL: store_undef_mask_factor2:
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; NEON: vst2.32 {d16, d17, d18, d19}, [r0]
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; NONEON-LABEL: store_undef_mask_factor2:
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; NONEON-NOT: vst2
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define void @store_undef_mask_factor2(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1) {
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%base = bitcast i32* %ptr to <8 x i32>*
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%interleaved.vec = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 6, i32 3, i32 7>
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store <8 x i32> %interleaved.vec, <8 x i32>* %base, align 4
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ret void
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}
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; NEON-LABEL: store_undef_mask_factor3:
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; NEON: vst3.32 {d16, d18, d20}, [r0]!
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; NEON: vst3.32 {d17, d19, d21}, [r0]
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; NONEON-LABEL: store_undef_mask_factor3:
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; NONEON-NOT: vst3
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define void @store_undef_mask_factor3(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2) {
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%base = bitcast i32* %ptr to <12 x i32>*
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%v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%v2_u = shufflevector <4 x i32> %v2, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
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%interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_u, <12 x i32> <i32 0, i32 4, i32 undef, i32 1, i32 undef, i32 9, i32 2, i32 6, i32 10, i32 3, i32 7, i32 11>
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store <12 x i32> %interleaved.vec, <12 x i32>* %base, align 4
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ret void
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}
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; NEON-LABEL: store_undef_mask_factor4:
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; NEON: vst4.32 {d16, d18, d20, d22}, [r0]!
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; NEON: vst4.32 {d17, d19, d21, d23}, [r0]
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; NONEON-LABEL: store_undef_mask_factor4:
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; NONEON-NOT: vst4
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define void @store_undef_mask_factor4(i32* %ptr, <4 x i32> %v0, <4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
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%base = bitcast i32* %ptr to <16 x i32>*
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%v0_v1 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%v2_v3 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%interleaved.vec = shufflevector <8 x i32> %v0_v1, <8 x i32> %v2_v3, <16 x i32> <i32 0, i32 4, i32 8, i32 undef, i32 undef, i32 5, i32 9, i32 13, i32 2, i32 6, i32 10, i32 14, i32 3, i32 7, i32 11, i32 15>
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store <16 x i32> %interleaved.vec, <16 x i32>* %base, align 4
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ret void
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}
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; The following test cases check that address spaces are properly handled
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; NEON-LABEL: load_address_space
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; NEON: vld3.32
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; NONEON-LABEL: load_address_space
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; NONEON-NOT: vld3
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define void @load_address_space(<4 x i32> addrspace(1)* %A, <2 x i32>* %B) {
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%tmp = load <4 x i32>, <4 x i32> addrspace(1)* %A
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%interleaved = shufflevector <4 x i32> %tmp, <4 x i32> undef, <2 x i32> <i32 0, i32 3>
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store <2 x i32> %interleaved, <2 x i32>* %B
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ret void
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}
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; NEON-LABEL: store_address_space
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; NEON: vst2.32
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; NONEON-LABEL: store_address_space
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; NONEON-NOT: vst2
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define void @store_address_space(<2 x i32>* %A, <2 x i32>* %B, <4 x i32> addrspace(1)* %C) {
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%tmp0 = load <2 x i32>, <2 x i32>* %A
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%tmp1 = load <2 x i32>, <2 x i32>* %B
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%interleaved = shufflevector <2 x i32> %tmp0, <2 x i32> %tmp1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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store <4 x i32> %interleaved, <4 x i32> addrspace(1)* %C
|
|
ret void
|
|
}
|
|
|
|
; Check that we do something sane with illegal types.
|
|
|
|
; NEON-LABEL: load_illegal_factor2:
|
|
; NEON: BB#0:
|
|
; NEON-NEXT: vld1.64 {d16, d17}, [r0:128]
|
|
; NEON-NEXT: vuzp.32 q8, {{.*}}
|
|
; NEON-NEXT: vmov r0, r1, d16
|
|
; NEON-NEXT: vmov r2, r3, {{.*}}
|
|
; NEON-NEXT: mov pc, lr
|
|
; NONEON-LABEL: load_illegal_factor2:
|
|
; NONEON: BB#0:
|
|
; NONEON-NEXT: ldr [[ELT0:r[0-9]+]], [r0]
|
|
; NONEON-NEXT: ldr r1, [r0, #8]
|
|
; NONEON-NEXT: mov r0, [[ELT0]]
|
|
; NONEON-NEXT: mov pc, lr
|
|
define <3 x float> @load_illegal_factor2(<3 x float>* %p) nounwind {
|
|
%tmp1 = load <3 x float>, <3 x float>* %p, align 16
|
|
%tmp2 = shufflevector <3 x float> %tmp1, <3 x float> undef, <3 x i32> <i32 0, i32 2, i32 undef>
|
|
ret <3 x float> %tmp2
|
|
}
|
|
|
|
; This lowering isn't great, but it's at least correct.
|
|
|
|
; NEON-LABEL: store_illegal_factor2:
|
|
; NEON: BB#0:
|
|
; NEON-NEXT: vldr d17, [sp]
|
|
; NEON-NEXT: vmov d16, r2, r3
|
|
; NEON-NEXT: vuzp.32 q8, {{.*}}
|
|
; NEON-NEXT: vstr d16, [r0]
|
|
; NEON-NEXT: mov pc, lr
|
|
; NONEON-LABEL: store_illegal_factor2:
|
|
; NONEON: BB#0:
|
|
; NONEON-NEXT: stm r0, {r1, r3}
|
|
; NONEON-NEXT: mov pc, lr
|
|
define void @store_illegal_factor2(<3 x float>* %p, <3 x float> %v) nounwind {
|
|
%tmp1 = shufflevector <3 x float> %v, <3 x float> undef, <3 x i32> <i32 0, i32 2, i32 undef>
|
|
store <3 x float> %tmp1, <3 x float>* %p, align 16
|
|
ret void
|
|
}
|
|
|
|
; NEON-LABEL: load_factor2_with_extract_user:
|
|
; NEON: vld2.32 {d16, d17, d18, d19}, [r0:64]
|
|
; NEON: vmov.32 r0, d16[1]
|
|
; NONEON-LABEL: load_factor2_with_extract_user:
|
|
; NONEON-NOT: vld2
|
|
define i32 @load_factor2_with_extract_user(<8 x i32>* %a) {
|
|
%1 = load <8 x i32>, <8 x i32>* %a, align 8
|
|
%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
|
|
%3 = extractelement <8 x i32> %1, i32 2
|
|
ret i32 %3
|
|
}
|