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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 02:52:53 +02:00
llvm-mirror/test
Craig Topper 9d2a7779c9 [X86] Use MOVZX instead of MOVSX in f16_to_fp isel patterns.
Using sign extend forces the adjacent element to either all zeros
or all ones. But all ones is a NAN. So that doesn't seem like a
great idea.

Trying to work on supporting this with strict FP where NAN would
definitely be bad.
2020-02-09 20:39:52 -08:00
..
Analysis [ConstantFold][NFC] Move scalable vector unit tests under vscale.ll 2020-02-05 16:03:51 -08:00
Assembler
Bindings
Bitcode Revert "[WPD/LowerTypeTests] Delay lowering/removal of type tests until after ICP" 2020-02-05 19:27:32 -08:00
BugPoint
CodeGen [X86] Use MOVZX instead of MOVSX in f16_to_fp isel patterns. 2020-02-09 20:39:52 -08:00
DebugInfo [DebugInfo]: Reorderd the emission of debug_str section. 2020-02-07 11:15:55 +05:30
Demangle
Examples
ExecutionEngine
Feature [LoopExtractor] Convert LoopExtractor from LoopPass to ModulePass 2020-02-09 12:25:21 +02:00
FileCheck Improve error message of FileCheck when stdin is empty 2020-02-04 11:14:55 +00:00
Instrumentation
Integer
JitListener
Linker Linker/module-max-warn.ll: Fix test to be compatible with Windows file separators 2020-02-07 17:14:05 -08:00
LTO [LTO] Add optimization remarks for removed functions 2020-01-29 15:53:51 -08:00
MachineVerifier
MC [AMDGPU] Use @LINE for error checking in gfx10 assembler tests 2020-02-07 18:27:07 +00:00
Object [llvm-readobj][test] - Cleanup testing of the --sections command line option. 2020-01-31 12:58:12 +03:00
ObjectYAML
Other [VectorCombine] new IR transform pass for partial vector ops 2020-02-09 10:04:41 -05:00
Reduce Revert "[llvm-reduce] add ReduceAttribute delta pass" 2020-02-05 14:15:11 -05:00
SafepointIRVerifier
Support
SymbolRewriter
TableGen [TableGen] Fix spurious type error in bit assignment. 2020-02-07 15:11:42 +00:00
ThinLTO/X86 [ThinLTO] Disable "Always import constants" due to compile time issues 2020-01-30 10:12:48 -08:00
tools [DebugInfo] Allow reading an address table with a mismatched address. 2020-02-08 20:00:03 +07:00
Transforms [VectorCombine] new IR transform pass for partial vector ops 2020-02-09 10:04:41 -05:00
Unit
Verifier Implement -fsemantic-interposition 2020-01-31 14:02:33 +01:00
YAMLParser
.clang-format
CMakeLists.txt [CMake] Fix accidentally inverted condition 2020-02-07 15:17:25 -08:00
lit.cfg.py
lit.site.cfg.py.in
TestRunner.sh