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f2011a3ae7
IMHO it is an antipattern to have a enum value that is Default. At any given piece of code it is not clear if we have to handle Default or if has already been mapped to a concrete value. In this case in particular, only the target can do the mapping and it is nice to make sure it is always done. This deletes the two default enum values of CodeModel and uses an explicit Optional<CodeModel> when it is possible that it is unspecified. llvm-svn: 309911
94 lines
3.1 KiB
C++
94 lines
3.1 KiB
C++
//===-- NVPTXTargetMachine.h - Define TargetMachine for NVPTX ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the NVPTX specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXTARGETMACHINE_H
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#define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETMACHINE_H
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#include "ManagedStringPool.h"
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#include "NVPTXSubtarget.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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/// NVPTXTargetMachine
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///
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class NVPTXTargetMachine : public LLVMTargetMachine {
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bool is64bit;
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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NVPTX::DrvInterface drvInterface;
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NVPTXSubtarget Subtarget;
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// Hold Strings that can be free'd all together with NVPTXTargetMachine
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ManagedStringPool ManagedStrPool;
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public:
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NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OP, bool is64bit);
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~NVPTXTargetMachine() override;
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const NVPTXSubtarget *getSubtargetImpl(const Function &) const override {
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return &Subtarget;
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}
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const NVPTXSubtarget *getSubtargetImpl() const { return &Subtarget; }
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bool is64Bit() const { return is64bit; }
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NVPTX::DrvInterface getDrvInterface() const { return drvInterface; }
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ManagedStringPool *getManagedStrPool() const {
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return const_cast<ManagedStringPool *>(&ManagedStrPool);
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}
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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// Emission of machine code through MCJIT is not supported.
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bool addPassesToEmitMC(PassManagerBase &, MCContext *&, raw_pwrite_stream &,
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bool = true) override {
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return true;
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}
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TargetLoweringObjectFile *getObjFileLowering() const override {
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return TLOF.get();
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}
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void adjustPassManager(PassManagerBuilder &) override;
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TargetIRAnalysis getTargetIRAnalysis() override;
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bool isMachineVerifierClean() const override {
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return false;
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}
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}; // NVPTXTargetMachine.
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class NVPTXTargetMachine32 : public NVPTXTargetMachine {
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virtual void anchor();
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public:
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NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT);
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};
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class NVPTXTargetMachine64 : public NVPTXTargetMachine {
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virtual void anchor();
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public:
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NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT);
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};
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} // end namespace llvm
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#endif
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