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https://github.com/RPCS3/llvm-mirror.git
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f56d44dbb2
Summary: * Similiar to the ARM backend yse the peephole optimizer to generate more conditional ALU operations; * Add predicated type with default always true to RR instructions in LanaiInstrInfo.td; * Move LanaiSetflagAluCombiner into optimizeCompare; * The ASM parser can currently only handle explicitly specified CC, so specify ".t" (true) where needed in the ASM test; * Remove unused MachineOperand flags; Reviewers: eliben Subscribers: aemerson Differential Revision: http://reviews.llvm.org/D22072 llvm-svn: 274807
110 lines
2.6 KiB
LLVM
110 lines
2.6 KiB
LLVM
; RUN: llc < %s -mtriple=lanai | FileCheck %s
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define i32 @f(i32 inreg %a, i32 inreg %b) nounwind ssp {
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entry:
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; CHECK-LABEL: f:
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; CHECK: sub.f %r6, %r7, [[IN:%.*]]
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; CHECK: sel.gt [[IN]], %r0, %rv
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%cmp = icmp sgt i32 %a, %b
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%sub = sub nsw i32 %a, %b
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%sub. = select i1 %cmp, i32 %sub, i32 0
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ret i32 %sub.
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}
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define i32 @g(i32 inreg %a, i32 inreg %b) nounwind ssp {
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entry:
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; CHECK-LABEL: g:
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; CHECK: sub.f %r7, %r6, [[IN:%.*]]
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; CHECK: sel.lt [[IN]], %r0, %rv
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%cmp = icmp slt i32 %a, %b
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%sub = sub nsw i32 %b, %a
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%sub. = select i1 %cmp, i32 %sub, i32 0
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ret i32 %sub.
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}
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define i32 @h(i32 inreg %a, i32 inreg %b) nounwind ssp {
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entry:
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; CHECK-LABEL: h:
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; CHECK: sub.f %r6, 0x3, [[IN:%.*]]
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; CHECK: sel.gt [[IN]], %r7, %rv
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%cmp = icmp sgt i32 %a, 3
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%sub = sub nsw i32 %a, 3
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%sub. = select i1 %cmp, i32 %sub, i32 %b
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ret i32 %sub.
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}
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define i32 @i(i32 inreg %a, i32 inreg %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: i:
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; CHECK: sub.f %r7, %r6, [[IN:%.*]]
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; CHECK: sel.ult [[IN]], %r0, %rv
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%cmp = icmp ult i32 %a, %b
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%sub = sub i32 %b, %a
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%sub. = select i1 %cmp, i32 %sub, i32 0
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ret i32 %sub.
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}
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; If SR is live-out, we can't remove cmp if there exists a swapped sub.
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define i32 @j(i32 inreg %a, i32 inreg %b) nounwind {
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entry:
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; CHECK-LABEL: j:
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; CHECK: sub.f %r7, %r6, %r0
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; CHECK: sub %r6, %r7, %rv
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%cmp = icmp eq i32 %b, %a
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%sub = sub nsw i32 %a, %b
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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%cmp2 = icmp sgt i32 %b, %a
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%sel = select i1 %cmp2, i32 %sub, i32 %a
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ret i32 %sel
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if.else:
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ret i32 %sub
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}
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declare void @abort()
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declare void @exit(i32)
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@t = common global i32 0
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; If the comparison uses the C bit (signed overflow/underflow), we can't
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; omit the comparison.
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define i32 @cmp_ult0(i32 inreg %a, i32 inreg %b, i32 inreg %x, i32 inreg %y) {
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entry:
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; CHECK-LABEL: cmp_ult0
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; CHECK: sub {{.*}}, 0x11, [[IN:%.*]]
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; CHECK: sub.f [[IN]], 0x0, %r0
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%load = load i32, i32* @t, align 4
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%sub = sub i32 %load, 17
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%cmp = icmp ult i32 %sub, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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call void @abort()
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unreachable
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if.else:
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call void @exit(i32 0)
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unreachable
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}
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; Same for the V bit.
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; TODO: add test that exercises V bit individually (VC/VS).
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define i32 @cmp_gt0(i32 inreg %a, i32 inreg %b, i32 inreg %x, i32 inreg %y) {
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entry:
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; CHECK-LABEL: cmp_gt0
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; CHECK: sub {{.*}}, 0x11, [[IN:%.*]]
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; CHECK: sub.f [[IN]], 0x1, %r0
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%load = load i32, i32* @t, align 4
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%sub = sub i32 %load, 17
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%cmp = icmp sgt i32 %sub, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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call void @abort()
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unreachable
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if.else:
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call void @exit(i32 0)
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unreachable
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}
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