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f61800be05
No changes relative to last time, but after a mitigation for an AMDGPU regression landed. --- If SimplifyInstruction() does not succeed in simplifying the instruction, it will compute the known bits of the instruction in the hope that all bits are known and the instruction can be folded to a constant. I have removed a similar optimization from InstCombine in D75801, and would like to drop this one as well. On average, we spend ~1% of total compile-time performing this known bits calculation. However, if we introduce some additional statistics for known bits computations and how many of them succeed in simplifying the instruction we get (on test-suite): instsimplify.NumKnownBits: 216 instsimplify.NumKnownBitsComputed: 13828375 valuetracking.NumKnownBitsComputed: 45860806 Out of ~14M known bits calculations (accounting for approximately one third of all known bits calculations), only 0.0015% succeed in producing a constant. Those cases where we do succeed to compute all known bits will get folded by other passes like InstCombine later. On test-suite, only lencod.test and GCC-C-execute-pr44858.test show a hash difference after this change. On lencod we see an improvement (a loop phi is optimized away), on the GCC torture test a regression (a function return value is determined only after IPSCCP, preventing propagation from a noinline function.) There are various regressions in InstSimplify tests. However, all of these cases are already handled by InstCombine, and corresponding tests have already been added there. Differential Revision: https://reviews.llvm.org/D79294
90 lines
2.6 KiB
LLVM
90 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -instsimplify -S < %s | FileCheck %s
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define i1 @test(i8 %p, i8* %pq) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: ret i1 false
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;
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%q = load i8, i8* %pq, !range !0 ; %q is known nonzero; no known bits
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%1 = or i8 %p, 2 ; %1[1] = 1
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%2 = and i8 %1, 254 ; %2[0] = 0, %2[1] = 1
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%A = lshr i8 %2, 1 ; We should know that %A is nonzero.
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%x = icmp eq i8 %A, 0
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ret i1 %x
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}
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!0 = !{ i8 1, i8 5 }
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; The following cases only get folded by InstCombine,
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; see InstCombine/shift-shift.ll. If we wanted to,
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; we could explicitly handle them in InstSimplify as well.
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define i32 @shl_shl(i32 %A) {
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; CHECK-LABEL: @shl_shl(
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; CHECK-NEXT: [[B:%.*]] = shl i32 [[A:%.*]], 6
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; CHECK-NEXT: [[C:%.*]] = shl i32 [[B]], 28
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; CHECK-NEXT: ret i32 [[C]]
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;
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%B = shl i32 %A, 6
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%C = shl i32 %B, 28
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ret i32 %C
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}
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define <2 x i33> @shl_shl_splat_vec(<2 x i33> %A) {
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; CHECK-LABEL: @shl_shl_splat_vec(
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; CHECK-NEXT: [[B:%.*]] = shl <2 x i33> [[A:%.*]], <i33 5, i33 5>
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; CHECK-NEXT: [[C:%.*]] = shl <2 x i33> [[B]], <i33 28, i33 28>
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; CHECK-NEXT: ret <2 x i33> [[C]]
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;
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%B = shl <2 x i33> %A, <i33 5, i33 5>
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%C = shl <2 x i33> %B, <i33 28, i33 28>
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ret <2 x i33> %C
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}
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; FIXME
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define <2 x i33> @shl_shl_vec(<2 x i33> %A) {
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; CHECK-LABEL: @shl_shl_vec(
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; CHECK-NEXT: [[B:%.*]] = shl <2 x i33> [[A:%.*]], <i33 6, i33 5>
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; CHECK-NEXT: [[C:%.*]] = shl <2 x i33> [[B]], <i33 27, i33 28>
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; CHECK-NEXT: ret <2 x i33> [[C]]
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;
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%B = shl <2 x i33> %A, <i33 6, i33 5>
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%C = shl <2 x i33> %B, <i33 27, i33 28>
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ret <2 x i33> %C
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}
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define i232 @lshr_lshr(i232 %A) {
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; CHECK-LABEL: @lshr_lshr(
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; CHECK-NEXT: [[B:%.*]] = lshr i232 [[A:%.*]], 231
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; CHECK-NEXT: [[C:%.*]] = lshr i232 [[B]], 1
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; CHECK-NEXT: ret i232 [[C]]
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;
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%B = lshr i232 %A, 231
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%C = lshr i232 %B, 1
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ret i232 %C
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}
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define <2 x i32> @lshr_lshr_splat_vec(<2 x i32> %A) {
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; CHECK-LABEL: @lshr_lshr_splat_vec(
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; CHECK-NEXT: [[B:%.*]] = lshr <2 x i32> [[A:%.*]], <i32 28, i32 28>
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; CHECK-NEXT: [[C:%.*]] = lshr <2 x i32> [[B]], <i32 4, i32 4>
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; CHECK-NEXT: ret <2 x i32> [[C]]
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;
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%B = lshr <2 x i32> %A, <i32 28, i32 28>
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%C = lshr <2 x i32> %B, <i32 4, i32 4>
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ret <2 x i32> %C
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}
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define <2 x i32> @lshr_lshr_vec(<2 x i32> %A) {
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; CHECK-LABEL: @lshr_lshr_vec(
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; CHECK-NEXT: [[B:%.*]] = lshr <2 x i32> [[A:%.*]], <i32 29, i32 28>
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; CHECK-NEXT: [[C:%.*]] = lshr <2 x i32> [[B]], <i32 4, i32 5>
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; CHECK-NEXT: ret <2 x i32> [[C]]
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;
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%B = lshr <2 x i32> %A, <i32 29, i32 28>
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%C = lshr <2 x i32> %B, <i32 4, i32 5>
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ret <2 x i32> %C
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}
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