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llvm-mirror/test/MC/AArch64/armv8.4a-trace-error.s
Sjoerd Meijer c3b59a654a [AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction
This adds the Armv8.4-A Trace synchronization barrier (TSB) instruction.

Differential Revision: https://reviews.llvm.org/D48918

llvm-svn: 336418
2018-07-06 08:03:12 +00:00

24 lines
728 B
ArmAsm

// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
//------------------------------------------------------------------------------
// ARMV8.4-A Debug, Trace and PMU Extensions
//------------------------------------------------------------------------------
tsb
tsb foo
tsb #0
tsb 0
//CHECK-ERROR: error: too few operands for instruction
//CHECK-ERROR: tsb
//CHECK-ERROR: ^
//CHECK-ERROR: error: 'csync' operand expected
//CHECK-ERROR: tsb foo
//CHECK-ERROR: ^
//CHECK-ERROR: error: 'csync' operand expected
//CHECK-ERROR: tsb #0
//CHECK-ERROR: ^
//CHECK-ERROR: error: 'csync' operand expected
//CHECK-ERROR: tsb 0
//CHECK-ERROR: ^