Evan Cheng 9e2442c0be Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g. ... vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0> => vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1> iff ptr is 16-byte aligned (or can be made into 16-byte aligned). llvm-svn: 90984		2009-12-09 21:00:30 +00:00
..
Alpha
ARM	- Support inline asm 'w' constraint for 128-bit vector types.	2009-12-08 23:06:22 +00:00
Blackfin
CBackend
CellSPU	Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 isl lowering code.	2009-12-09 01:53:58 +00:00
CPP	fix PR5295 where the .ll parser didn't reject a function after a global	2009-10-25 23:22:50 +00:00
Generic	While this test is testing a problem in the generic part of codegen,	2009-11-27 16:04:14 +00:00
Mips	Support PIC loading of constant pool entries	2009-11-25 12:17:58 +00:00
MSP430	Reduce (cmp 0, and_su (foo, bar)) into (bit foo, bar). This saves extra instruction. Patch inspired by Brian Lucas!	2009-12-08 01:03:04 +00:00
PIC16	While this test is testing a problem in the generic part of codegen,	2009-11-27 16:04:14 +00:00
PowerPC	ProcessImplicitDefs should watch out for invalidated iterator and extra implicit operands on copies.	2009-11-25 21:13:39 +00:00
SPARC
SystemZ
Thumb	More consistent thumb1 asm printing.	2009-11-19 06:57:41 +00:00
Thumb2	Dynamic stack realignment use of sp register as source/dest register	2009-12-06 22:39:50 +00:00
X86	Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g.	2009-12-09 21:00:30 +00:00
XCore	Add XCore support for indirectbr / blockaddress.	2009-11-18 23:20:42 +00:00