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f83cdf3d18
replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE when recursively updating nodes. Since OpA has been processed, the new uses are not examined again. The patch checks if this occurred and it it did, updates the new uses of OpA to use OpB. llvm-svn: 105453
47 lines
2.3 KiB
LLVM
47 lines
2.3 KiB
LLVM
; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s
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; widening shuffle v3float and then a add
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define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
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entry:
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; CHECK: insertps
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; CHECK: extractps
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%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 1, i32 2>
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%val = fadd <3 x float> %x, %src2
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store <3 x float> %val, <3 x float>* %dst.addr
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ret void
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}
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; widening shuffle v3float with a different mask and then a add
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define void @shuf2(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
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entry:
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; CHECK: insertps
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; CHECK: extractps
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%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 4, i32 2>
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%val = fadd <3 x float> %x, %src2
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store <3 x float> %val, <3 x float>* %dst.addr
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ret void
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}
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; Example of when widening a v3float operation causes the DAG to replace a node
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; with the operation that we are currently widening, i.e. when replacing
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; opA with opB, the DAG will produce new operations with opA.
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define void @shuf3(<4 x float> %tmp10, <4 x float> %vecinit15, <4 x float>* %dst) {
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entry:
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; CHECK: pshufd
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%shuffle.i.i.i12 = shufflevector <4 x float> %tmp10, <4 x float> %vecinit15, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
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%tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
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%tmp1.i.i = shufflevector <3 x float> %tmp25.i.i, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%tmp3.i13 = shufflevector <4 x float> %tmp1.i.i, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> ; <<3 x float>>
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%tmp6.i14 = shufflevector <3 x float> %tmp3.i13, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%tmp97.i = shufflevector <4 x float> %tmp6.i14, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
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%tmp2.i18 = shufflevector <3 x float> %tmp97.i, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
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%t5 = bitcast <4 x float> %tmp2.i18 to <4 x i32>
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%shr.i.i19 = lshr <4 x i32> %t5, <i32 19, i32 19, i32 19, i32 19>
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%and.i.i20 = and <4 x i32> %shr.i.i19, <i32 4080, i32 4080, i32 4080, i32 4080>
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%shuffle.i.i.i21 = shufflevector <4 x float> %tmp2.i18, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
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store <4 x float> %shuffle.i.i.i21, <4 x float>* %dst
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ret void
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}
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