mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
c43ce3d9fa
For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC,
get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs.
For MIPS, only the DSP ASE has a carry flag, so in the general case it is not
useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes.
Also improve the generation code in such cases for targets with
TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the
comparison node rather than using it in selects. Similarly for ISD::SUBE /
ISD::SUBC.
Address optimization breakage by moving the generation of MIPS specific integer
multiply-accumulate nodes to before legalization.
This revolves PR32713 and PR33424.
Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue!
Reviewers: slthakur
Differential Revision: https://reviews.llvm.org/D33494
The previous version of this patch was too aggressive in producing fused
integer multiple-addition instructions.
llvm-svn: 307906
24 lines
408 B
LLVM
24 lines
408 B
LLVM
; RUN: llc -march=mips < %s | FileCheck %s
|
|
|
|
define i64 @add64(i64 %u, i64 %v) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: add64:
|
|
; CHECK: addu
|
|
; CHECK-DAG: sltu
|
|
; CHECK-DAG: addu
|
|
; CHECK: addu
|
|
%tmp2 = add i64 %u, %v
|
|
ret i64 %tmp2
|
|
}
|
|
|
|
define i64 @sub64(i64 %u, i64 %v) nounwind {
|
|
entry:
|
|
; CHECK-LABEL: sub64
|
|
; CHECK-DAG: sltu
|
|
; CHECK-DAG: subu
|
|
; CHECK: subu
|
|
; CHECK: subu
|
|
%tmp2 = sub i64 %u, %v
|
|
ret i64 %tmp2
|
|
}
|