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https://github.com/RPCS3/llvm-mirror.git
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8d51bb5b3b
Fast-isel was picking AFGR64 register class for processing call arguments when +fp64 options was used. We simply check is option +fp64 is used and pick appropriate register. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D65886 llvm-svn: 368433
30 lines
1.2 KiB
LLVM
30 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -march=mips -mcpu=mips32r2 -O0 -relocation-model=pic -mattr=+fp64 \
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; RUN: -stop-before=prologepilog %s -o - | FileCheck %s
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declare double @bar(double)
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define double @foo(double %self) {
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; CHECK-LABEL: name: foo
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; CHECK: bb.0.start:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $d12_64, $t9, $v0
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; CHECK: renamable $at = ADDu killed $v0, killed $t9
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; CHECK: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
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; CHECK: $d6_64 = COPY killed renamable $d12_64
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; CHECK: renamable $t9 = LW killed renamable $at, target-flags(mips-got) @bar
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; CHECK: dead $ra = JALR killed $t9, csr_o32_fp64, target-flags(mips-jalr) <mcsymbol bar>, implicit-def dead $ra, implicit killed $d6_64, implicit-def $d0_64
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; CHECK: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
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; CHECK: SDC164 killed $d0_64, %stack.0, 0 :: (store 8 into %stack.0)
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; CHECK: bb.1.bb1:
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; CHECK: $d0_64 = LDC164 %stack.0, 0 :: (load 8 from %stack.0)
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; CHECK: RetRA implicit killed $d0_64
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start:
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%0 = call double @bar(double %self)
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br label %bb1
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bb1:
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ret double %0
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}
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