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961f3df27b
As part of the unification of the debug format and the MIR format, always print registers as lowercase. * Only debug printing is affected. It now follows MIR. Differential Revision: https://reviews.llvm.org/D40417 llvm-svn: 319187
28 lines
903 B
LLVM
28 lines
903 B
LLVM
; RUN: llc < %s -mtriple=i386-apple-darwin9 -O0 -optimize-regalloc -regalloc=basic -no-integrated-as | FileCheck %s
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; rdar://6992609
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target triple = "i386-apple-darwin9.0"
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define i64 @_OSSwapInt64(i64 %_data) nounwind {
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entry:
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%0 = call i64 asm "bswap %eax\0A\09bswap %edx\0A\09xchgl %eax, %%edx", "=A,0,~{dirflag},~{fpsr},~{flags}"(i64 %_data) nounwind
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ret i64 %0
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}
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; CHECK-LABEL: __OSSwapInt64:
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; CHECK-DAG: movl 8(%esp), %edx
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; CHECK-DAG: movl 4(%esp), %eax
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; CHECK: ## InlineAsm Start
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; CHECK: ## InlineAsm End
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; Everything is set up in eax:edx, return immediately.
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; CHECK-NEXT: retl
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; The tied operands are not necessarily in the same order as the defs.
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; PR13742
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define i64 @swapped(i64 %x, i64 %y) nounwind {
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entry:
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%x0 = call { i64, i64 } asm "foo", "=r,=r,1,0,~{dirflag},~{fpsr},~{flags}"(i64 %x, i64 %y) nounwind
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%x1 = extractvalue { i64, i64 } %x0, 0
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ret i64 %x1
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}
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