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https://github.com/RPCS3/llvm-mirror.git
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2f76252b8b
Summary: EmitTest sometimes creates X86ISD::AND specifically to hide the AND from DAG combine. But this prevents isel patterns that look for (cmp (and X, Y), 0) from being able to see it. So we end up with an AND and a TEST. The TEST gets removed by compare instruction optimization during the peephole pass. This patch attempts to fix this by converting X86ISD::AND with no flag users back into ISD::AND during the DAG preprocessing just before isel. In order to do this correctly I had to make the X86ISD::AND node created by EmitTest in this case really have a flag output. Which arguably it should have had anyway so that the number of operands would be consistent for the opcode in all cases. Then I had to modify the ReplaceAllUsesWith to understand that we might be looking at an instruction with 2 outputs. Though in this case there are no uses to replace since we just created the node, but that's what the code did before so I just made it keep working. Reviewers: spatel, RKSimon, niravd, deadalnix Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42764 llvm-svn: 323982
434 lines
12 KiB
LLVM
434 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=cmov -verify-machineinstrs | FileCheck %s
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define i32 @func_f(i32 %X) {
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; CHECK-LABEL: func_f:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: incl %eax
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; CHECK-NEXT: jns .LBB0_2
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; CHECK-NEXT: # %bb.1: # %cond_true
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; CHECK-NEXT: calll bar
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; CHECK-NEXT: .LBB0_2: # %cond_next
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; CHECK-NEXT: jmp baz # TAILCALL
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entry:
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%tmp1 = add i32 %X, 1
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%tmp = icmp slt i32 %tmp1, 0
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br i1 %tmp, label %cond_true, label %cond_next, !prof !1
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cond_true: ; preds = %entry
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%tmp2 = tail call i32 (...) @bar( )
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br label %cond_next
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cond_next: ; preds = %cond_true, %entry
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%tmp3 = tail call i32 (...) @baz( )
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ret i32 undef
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}
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declare i32 @bar(...)
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declare i32 @baz(...)
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; rdar://10633221
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; rdar://11355268
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define i32 @func_g(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: func_g:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: subl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: cmovsl %ecx, %eax
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; CHECK-NEXT: retl
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%sub = sub nsw i32 %a, %b
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%cmp = icmp sgt i32 %sub, 0
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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; rdar://10734411
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define i32 @func_h(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: func_h:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: subl %ecx, %eax
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; CHECK-NEXT: cmovlel %edx, %eax
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; CHECK-NEXT: retl
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%cmp = icmp slt i32 %b, %a
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%sub = sub nsw i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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define i32 @func_i(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: func_i:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: subl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: cmovlel %ecx, %eax
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; CHECK-NEXT: retl
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%cmp = icmp sgt i32 %a, %b
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%sub = sub nsw i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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define i32 @func_j(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: func_j:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: subl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: cmovbel %ecx, %eax
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; CHECK-NEXT: retl
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%cmp = icmp ugt i32 %a, %b
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%sub = sub i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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define i32 @func_k(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: func_k:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: subl %ecx, %eax
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; CHECK-NEXT: cmovbel %edx, %eax
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; CHECK-NEXT: retl
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%cmp = icmp ult i32 %b, %a
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%sub = sub i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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; redundant cmp instruction
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define i32 @func_l(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: func_l:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
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; CHECK-NEXT: movl %edx, %eax
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; CHECK-NEXT: subl %ecx, %eax
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; CHECK-NEXT: cmovlel %edx, %eax
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; CHECK-NEXT: retl
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%cmp = icmp slt i32 %b, %a
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%sub = sub nsw i32 %a, %b
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%cond = select i1 %cmp, i32 %sub, i32 %a
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ret i32 %cond
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}
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define i32 @func_m(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: func_m:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: subl %ecx, %eax
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; CHECK-NEXT: cmovgl %ecx, %eax
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; CHECK-NEXT: retl
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%cmp = icmp sgt i32 %a, %b
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%sub = sub nsw i32 %a, %b
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%cond = select i1 %cmp, i32 %b, i32 %sub
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ret i32 %cond
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}
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; If EFLAGS is live-out, we can't remove cmp if there exists
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; a swapped sub.
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define i32 @func_l2(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: func_l2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl %eax, %ecx
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; CHECK-NEXT: subl %edx, %ecx
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; CHECK-NEXT: cmpl %eax, %edx
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; CHECK-NEXT: jne .LBB8_2
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; CHECK-NEXT: # %bb.1: # %if.then
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; CHECK-NEXT: cmovgl %ecx, %eax
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB8_2: # %if.else
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; CHECK-NEXT: movl %ecx, %eax
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; CHECK-NEXT: retl
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%cmp = icmp eq i32 %b, %a
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%sub = sub nsw i32 %a, %b
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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%cmp2 = icmp sgt i32 %b, %a
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%sel = select i1 %cmp2, i32 %sub, i32 %a
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ret i32 %sel
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if.else:
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ret i32 %sub
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}
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define i32 @func_l3(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: func_l3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: subl %ecx, %eax
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; CHECK-NEXT: jge .LBB9_2
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; CHECK-NEXT: # %bb.1: # %if.then
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB9_2: # %if.else
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; CHECK-NEXT: incl %eax
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; CHECK-NEXT: retl
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%cmp = icmp sgt i32 %b, %a
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%sub = sub nsw i32 %a, %b
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br i1 %cmp, label %if.then, label %if.else
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if.then:
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ret i32 %sub
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if.else:
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%add = add nsw i32 %sub, 1
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ret i32 %add
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}
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; rdar://11830760
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; When Movr0 is between sub and cmp, we need to move "Movr0" before sub.
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define i32 @func_l4(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: func_l4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: subl %ecx, %eax
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; CHECK-NEXT: cmovll %edx, %eax
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; CHECK-NEXT: retl
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%cmp = icmp sgt i32 %b, %a
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%sub = sub i32 %a, %b
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%.sub = select i1 %cmp, i32 0, i32 %sub
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ret i32 %.sub
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}
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; rdar://11540023
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define i32 @func_n(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: func_n:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: cmpl %ecx, %eax
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; CHECK-NEXT: cmovsl %ecx, %eax
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; CHECK-NEXT: retl
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%sub = sub nsw i32 %x, %y
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%cmp = icmp slt i32 %sub, 0
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%y.x = select i1 %cmp, i32 %y, i32 %x
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ret i32 %y.x
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}
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; PR://13046
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define void @func_o() nounwind uwtable {
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; CHECK-LABEL: func_o:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: je .LBB12_1
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; CHECK-NEXT: # %bb.2: # %if.end.i
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: jne .LBB12_5
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; CHECK-NEXT: # %bb.3: # %sw.bb
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: jne .LBB12_8
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; CHECK-NEXT: # %bb.4: # %if.end29
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; CHECK-NEXT: movzwl (%eax), %eax
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; CHECK-NEXT: movzwl %ax, %eax
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; CHECK-NEXT: imull $52429, %eax, %ecx # imm = 0xCCCD
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; CHECK-NEXT: shrl $19, %ecx
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; CHECK-NEXT: addl %ecx, %ecx
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; CHECK-NEXT: leal (%ecx,%ecx,4), %ecx
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; CHECK-NEXT: cmpw %cx, %ax
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; CHECK-NEXT: jne .LBB12_5
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; CHECK-NEXT: .LBB12_8: # %if.then44
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: je .LBB12_9
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; CHECK-NEXT: # %bb.10: # %if.else.i104
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB12_5: # %sw.default
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: jne .LBB12_7
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; CHECK-NEXT: # %bb.6: # %if.then.i96
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; CHECK-NEXT: .LBB12_1: # %if.then.i
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; CHECK-NEXT: .LBB12_9: # %if.then.i103
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; CHECK-NEXT: .LBB12_7: # %if.else.i97
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entry:
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%0 = load i16, i16* undef, align 2
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br i1 undef, label %if.then.i, label %if.end.i
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if.then.i: ; preds = %entry
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unreachable
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if.end.i: ; preds = %entry
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br i1 undef, label %sw.bb, label %sw.default
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sw.bb: ; preds = %if.end.i
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br i1 undef, label %if.then44, label %if.end29
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if.end29: ; preds = %sw.bb
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%1 = urem i16 %0, 10
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%cmp25 = icmp eq i16 %1, 0
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%. = select i1 %cmp25, i16 2, i16 0
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br i1 %cmp25, label %if.then44, label %sw.default
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sw.default: ; preds = %if.end29, %if.end.i
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br i1 undef, label %if.then.i96, label %if.else.i97
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if.then.i96: ; preds = %sw.default
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unreachable
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if.else.i97: ; preds = %sw.default
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unreachable
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if.then44: ; preds = %if.end29, %sw.bb
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%aModeRefSel.1.ph = phi i16 [ %., %if.end29 ], [ 3, %sw.bb ]
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br i1 undef, label %if.then.i103, label %if.else.i104
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if.then.i103: ; preds = %if.then44
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unreachable
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if.else.i104: ; preds = %if.then44
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ret void
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}
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; rdar://11855129
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define i32 @func_p(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: func_p:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: cmovsl %ecx, %eax
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; CHECK-NEXT: retl
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%add = add nsw i32 %b, %a
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%cmp = icmp sgt i32 %add, 0
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%add. = select i1 %cmp, i32 %add, i32 0
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ret i32 %add.
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}
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; PR13475
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; If we have sub a, b and cmp b, a and the result of cmp is used
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; by sbb, we should not optimize cmp away.
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define i32 @func_q(i32 %a0, i32 %a1, i32 %a2) {
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; CHECK-LABEL: func_q:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movl %ecx, %edx
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; CHECK-NEXT: subl %eax, %edx
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; CHECK-NEXT: cmpl %ecx, %eax
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; CHECK-NEXT: sbbl %eax, %eax
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; CHECK-NEXT: xorl %edx, %eax
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; CHECK-NEXT: retl
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%t1 = icmp ult i32 %a0, %a1
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%t2 = sub i32 %a1, %a0
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%t3 = select i1 %t1, i32 -1, i32 0
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%t4 = xor i32 %t2, %t3
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ret i32 %t4
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}
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; rdar://11873276
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define i8* @func_r(i8* %base, i32* nocapture %offset, i32 %size) nounwind {
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; CHECK-LABEL: func_r:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
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; CHECK-NEXT: movl (%edx), %ecx
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: subl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: jl .LBB15_2
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; CHECK-NEXT: # %bb.1: # %if.end
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl %ecx, (%edx)
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; CHECK-NEXT: addl %ecx, %eax
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; CHECK-NEXT: .LBB15_2: # %return
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; CHECK-NEXT: retl
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entry:
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%0 = load i32, i32* %offset, align 8
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%cmp = icmp slt i32 %0, %size
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br i1 %cmp, label %return, label %if.end
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if.end:
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%sub = sub nsw i32 %0, %size
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store i32 %sub, i32* %offset, align 8
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%add.ptr = getelementptr inbounds i8, i8* %base, i32 %sub
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br label %return
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return:
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%retval.0 = phi i8* [ %add.ptr, %if.end ], [ null, %entry ]
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ret i8* %retval.0
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}
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; Test optimizations of dec/inc.
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define i32 @func_dec(i32 %a) nounwind {
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; CHECK-LABEL: func_dec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: decl %eax
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; CHECK-NEXT: cmovsl %ecx, %eax
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; CHECK-NEXT: retl
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%sub = sub nsw i32 %a, 1
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%cmp = icmp sgt i32 %sub, 0
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%cond = select i1 %cmp, i32 %sub, i32 0
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ret i32 %cond
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}
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define i32 @func_inc(i32 %a) nounwind {
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; CHECK-LABEL: func_inc:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: incl %eax
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; CHECK-NEXT: cmovsl %ecx, %eax
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; CHECK-NEXT: retl
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%add = add nsw i32 %a, 1
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%cmp = icmp sgt i32 %add, 0
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%cond = select i1 %cmp, i32 %add, i32 0
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ret i32 %cond
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}
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; PR13966
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@b = common global i32 0, align 4
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@a = common global i32 0, align 4
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define i32 @func_test1(i32 %p1) nounwind uwtable {
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; CHECK-LABEL: func_test1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl b, %eax
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; CHECK-NEXT: cmpl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: setb %cl
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; CHECK-NEXT: movl a, %eax
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; CHECK-NEXT: testb %al, %cl
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; CHECK-NEXT: je .LBB18_2
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; CHECK-NEXT: # %bb.1: # %if.then
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|
; CHECK-NEXT: decl %eax
|
|
; CHECK-NEXT: movl %eax, a
|
|
; CHECK-NEXT: .LBB18_2: # %if.end
|
|
; CHECK-NEXT: retl
|
|
entry:
|
|
%t0 = load i32, i32* @b, align 4
|
|
%cmp = icmp ult i32 %t0, %p1
|
|
%conv = zext i1 %cmp to i32
|
|
%t1 = load i32, i32* @a, align 4
|
|
%and = and i32 %conv, %t1
|
|
%conv1 = trunc i32 %and to i8
|
|
%t2 = urem i8 %conv1, 3
|
|
%tobool = icmp eq i8 %t2, 0
|
|
br i1 %tobool, label %if.end, label %if.then
|
|
|
|
if.then:
|
|
%dec = add nsw i32 %t1, -1
|
|
store i32 %dec, i32* @a, align 4
|
|
br label %if.end
|
|
|
|
if.end:
|
|
ret i32 undef
|
|
}
|
|
|
|
!1 = !{!"branch_weights", i32 2, i32 1}
|
|
|