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f7935a3f63
`llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309774
58 lines
1.9 KiB
LLVM
58 lines
1.9 KiB
LLVM
; RUN: llc < %s -mtriple=i686-- -mattr=+mmx,+sse,+soft-float \
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; RUN: | FileCheck %s --check-prefix=SOFT1 --check-prefix=CHECK
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+mmx,+sse2,+soft-float \
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; RUN: | FileCheck %s --check-prefix=SOFT2 --check-prefix=CHECK
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+mmx,+sse \
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; RUN: | FileCheck %s --check-prefix=SSE1 --check-prefix=CHECK
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+mmx,+sse2 \
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; RUN: | FileCheck %s --check-prefix=SSE2 --check-prefix=CHECK
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; RUN: llc < %s -mtriple=x86_64-gnux32 -mattr=+mmx,+sse2,+soft-float | FileCheck %s
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; CHECK-NOT: xmm{{[0-9]+}}
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%struct.__va_list_tag = type { i32, i32, i8*, i8* }
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define i32 @t1(i32 %a, ...) nounwind {
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entry:
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%va = alloca [1 x %struct.__va_list_tag], align 8 ; <[1 x %struct.__va_list_tag]*> [#uses=2]
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%va12 = bitcast [1 x %struct.__va_list_tag]* %va to i8* ; <i8*> [#uses=2]
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call void @llvm.va_start(i8* %va12)
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%va3 = getelementptr [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %va, i64 0, i64 0 ; <%struct.__va_list_tag*> [#uses=1]
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call void @bar(%struct.__va_list_tag* %va3) nounwind
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call void @llvm.va_end(i8* %va12)
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ret i32 undef
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; CHECK-LABEL: t1:
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; CHECK: ret{{[lq]}}
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}
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declare void @llvm.va_start(i8*) nounwind
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declare void @bar(%struct.__va_list_tag*)
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declare void @llvm.va_end(i8*) nounwind
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define float @t2(float %a, float %b) nounwind readnone {
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entry:
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%0 = fadd float %a, %b ; <float> [#uses=1]
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ret float %0
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; CHECK-LABEL: t2:
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; SOFT1-NOT: xmm{{[0-9]+}}
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; SOFT2-NOT: xmm{{[0-9]+}}
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; SSE1: xmm{{[0-9]+}}
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; SSE2: xmm{{[0-9]+}}
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; CHECK: ret{{[lq]}}
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}
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; soft-float means no SSE instruction and passing fp128 as pair of i64.
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define fp128 @t3(fp128 %a, fp128 %b) nounwind readnone {
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entry:
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%0 = fadd fp128 %b, %a
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ret fp128 %0
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; CHECK-LABEL: t3:
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; SOFT1-NOT: xmm{{[0-9]+}}
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; SOFT2-NOT: xmm{{[0-9]+}}
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; SSE1: xmm{{[0-9]+}}
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; SSE2: xmm{{[0-9]+}}
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; CHECK: ret{{[lq]}}
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}
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