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30264d4391
As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
105 lines
3.4 KiB
LLVM
105 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X64
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; When loading the shift amount from memory, avoid generating the splat.
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define void @shift5a(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
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; X32-LABEL: shift5a:
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; X32: # %bb.0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X32-NEXT: pslld %xmm1, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift5a:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X64-NEXT: pslld %xmm1, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%amt = load i32, i32* %pamt
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%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
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%shl = shl <4 x i32> %val, %shamt
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store <4 x i32> %shl, <4 x i32>* %dst
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ret void
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}
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define void @shift5b(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
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; X32-LABEL: shift5b:
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; X32: # %bb.0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X32-NEXT: psrad %xmm1, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift5b:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X64-NEXT: psrad %xmm1, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%amt = load i32, i32* %pamt
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%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
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%shr = ashr <4 x i32> %val, %shamt
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store <4 x i32> %shr, <4 x i32>* %dst
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ret void
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}
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define void @shift5c(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
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; X32-LABEL: shift5c:
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; X32: # %bb.0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X32-NEXT: pslld %xmm1, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift5c:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movd %esi, %xmm1
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; X64-NEXT: pslld %xmm1, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
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%shl = shl <4 x i32> %val, %shamt
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store <4 x i32> %shl, <4 x i32>* %dst
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ret void
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}
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define void @shift5d(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
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; X32-LABEL: shift5d:
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; X32: # %bb.0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X32-NEXT: psrad %xmm1, %xmm0
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; X32-NEXT: movdqa %xmm0, (%eax)
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; X32-NEXT: retl
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;
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; X64-LABEL: shift5d:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movd %esi, %xmm1
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; X64-NEXT: psrad %xmm1, %xmm0
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; X64-NEXT: movdqa %xmm0, (%rdi)
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; X64-NEXT: retq
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entry:
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%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
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%shr = ashr <4 x i32> %val, %shamt
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store <4 x i32> %shr, <4 x i32>* %dst
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ret void
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}
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