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2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
28 lines
823 B
LLVM
28 lines
823 B
LLVM
; RUN: llc < %s -march=arm64 | FileCheck %s
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define void @t1(i8* nocapture %c) nounwind optsize {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: str wzr, [x0, #8]
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; CHECK: str xzr, [x0]
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call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 12, i32 8, i1 false)
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ret void
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}
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define void @t2() nounwind ssp {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: strh wzr, [sp, #32]
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; CHECK: stp xzr, xzr, [sp, #16]
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; CHECK: str xzr, [sp, #8]
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%buf = alloca [26 x i8], align 1
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%0 = getelementptr inbounds [26 x i8]* %buf, i32 0, i32 0
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call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i32 1, i1 false)
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call void @something(i8* %0) nounwind
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ret void
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}
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declare void @something(i8*) nounwind
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declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
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