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2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
18 lines
737 B
LLVM
18 lines
737 B
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
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; LowerCONCAT_VECTORS() was reversing the order of two parts.
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; rdar://11558157
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; rdar://11559553
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define <16 x i8> @test(<16 x i8> %q0, <16 x i8> %q1, i8* nocapture %dest) nounwind {
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entry:
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; CHECK-LABEL: test:
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; CHECK: ins.d v0[1], v1[0]
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%0 = bitcast <16 x i8> %q0 to <2 x i64>
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%shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> zeroinitializer
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%1 = bitcast <16 x i8> %q1 to <2 x i64>
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%shuffle.i4 = shufflevector <2 x i64> %1, <2 x i64> undef, <1 x i32> zeroinitializer
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%shuffle.i3 = shufflevector <1 x i64> %shuffle.i, <1 x i64> %shuffle.i4, <2 x i32> <i32 0, i32 1>
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%2 = bitcast <2 x i64> %shuffle.i3 to <16 x i8>
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ret <16 x i8> %2
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}
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