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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
llvm-mirror/test/CodeGen
Reed Kotler 9f4f45f079 Make first substantial checkin of my port of ARM constant islands code to Mips.
Before I just ported the shell of the pass. I've tried to keep everything
nearly identical to the ARM version. I think it will be very easy to eventually
merge these two and create a new more general pass that other targets can
use. I have some improvements I would like to make to allow pools to 
be shared across functions and some other things. When I'm all done we
can think about making a more general pass. More to be ported but the
basic mechanism works now almost as good as gcc mips16.

llvm-svn: 193509
2013-10-27 21:57:36 +00:00
..
AArch64 [AArch64] Fix NZCV reg live-in bug in F128CSEL codegen. 2013-10-24 08:28:24 +00:00
ARM ARM: don't expand atomicrmw inline on Cortex-M0 2013-10-25 09:30:24 +00:00
CPP
Generic
Hexagon
Inputs
Mips Make first substantial checkin of my port of ARM constant islands code to Mips. 2013-10-27 21:57:36 +00:00
MSP430 Make sure SP is always aligned on a 2 byte boundary 2013-10-24 09:32:31 +00:00
NVPTX
PowerPC Update PPC loop tests after SCEV non-unit-stride checkin r193015. 2013-10-19 00:14:04 +00:00
R600 R600/SI: fix MIMG writemask adjustement 2013-10-23 02:53:47 +00:00
SPARC
SystemZ Replace sra with srl if a single sign bit is required 2013-10-17 11:16:57 +00:00
Thumb 17309 ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets 2013-10-17 19:52:05 +00:00
Thumb2 MachineSink: Fix and tweak critical-edge breaking heuristic. 2013-10-14 16:57:17 +00:00
X86 AVX-512: PMIN/PMAX intrinsics and patterns 2013-10-27 08:18:37 +00:00
XCore