mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-26 04:32:44 +01:00
dd53274771
This reverts commit 80a34ae31125aa46dcad47162ba45b152aed968d with fixes. Previously, since bots turning on EXPENSIVE_CHECKS are essentially turning on MachineVerifierPass by default on X86 and the fact that inline-asm-avx-v-constraint-32bit.ll and inline-asm-avx512vl-v-constraint-32bit.ll are not expected to generate functioning machine code, this would go down to `report_fatal_error` in MachineVerifierPass. Here passing `-verify-machineinstrs=0` to make the intent explicit.
55 lines
1.7 KiB
YAML
55 lines
1.7 KiB
YAML
# RUN: not --crash llc -verify-machineinstrs -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
|
|
# REQUIRES: global-isel, aarch64-registered-target
|
|
|
|
--- |
|
|
|
|
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
|
|
target triple = "aarch64--"
|
|
define void @test() { ret void }
|
|
|
|
...
|
|
|
|
---
|
|
name: test
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: gpr }
|
|
- { id: 3, class: gpr }
|
|
- { id: 4, class: gpr }
|
|
- { id: 5, class: gpr }
|
|
- { id: 6, class: gpr }
|
|
- { id: 7, class: gpr }
|
|
body: |
|
|
bb.0:
|
|
liveins: $x0
|
|
%0(s64) = COPY $x0
|
|
%1(<4 x s16>) = COPY $x0
|
|
|
|
; CHECK: *** Bad machine code: G_SEXT_INREG expects an immediate operand #2 ***
|
|
; CHECK: instruction: %2:gpr(s64) = G_SEXT_INREG
|
|
%2(s64) = G_SEXT_INREG %0, %0
|
|
|
|
; CHECK: *** Bad machine code: G_SEXT_INREG expects an immediate operand #2 ***
|
|
; CHECK: instruction: %3:gpr(s64) = G_SEXT_INREG
|
|
%3(s64) = G_SEXT_INREG %0, i8 8
|
|
|
|
; CHECK: *** Bad machine code: Type mismatch in generic instruction ***
|
|
; CHECK: instruction: %4:gpr(<2 x s32>) = G_SEXT_INREG
|
|
; CHECK: *** Bad machine code: operand types must be all-vector or all-scalar ***
|
|
; CHECK: instruction: %4:gpr(<2 x s32>) = G_SEXT_INREG
|
|
%4(<2 x s32>) = G_SEXT_INREG %0, 8
|
|
|
|
; CHECK: *** Bad machine code: operand types must preserve number of vector elements ***
|
|
; CHECK: instruction: %5:gpr(<2 x s32>) = G_SEXT_INREG
|
|
%5(<2 x s32>) = G_SEXT_INREG %1, 8
|
|
|
|
; CHECK: *** Bad machine code: G_SEXT_INREG size must be >= 1 ***
|
|
; CHECK: instruction: %6:gpr(s64) = G_SEXT_INREG
|
|
%6(s64) = G_SEXT_INREG %0, 0
|
|
|
|
; CHECK: *** Bad machine code: G_SEXT_INREG size must be less than source bit width ***
|
|
; CHECK: instruction: %7:gpr(s64) = G_SEXT_INREG
|
|
%7(s64) = G_SEXT_INREG %0, 128
|
|
...
|