Matt Arsenault 53cca02b90 GlobalISel: Verify G_BITCAST changes the type ... Updated the AArch64 tests the best I could with my vague, inferred understanding of AArch64 register banks. As far as I can tell, there is only one 32-bit/64-bit type which will use the gpr register bank, so we have to use the fpr bank for the other operand.		2020-07-08 17:16:27 -04:00
..
generic-vreg-undef-use.mir	GlobalISel: Disallow undef generic virtual register uses	2020-06-30 19:18:01 -04:00
live-ins-01.mir
live-ins-02.mir
live-ins-03.mir
test_copy_mismatch_types.mir
test_copy.mir
test_g_add.mir
test_g_addrspacecast.mir
test_g_bitcast.mir	GlobalISel: Verify G_BITCAST changes the type	2020-07-08 17:16:27 -04:00
test_g_brindirect_is_indirect_branch.mir	[NFC] Remove unnecessary require global-isel from tests	2020-06-15 16:35:18 +02:00
test_g_brjt_is_indirect_branch.mir	[NFC] Remove unnecessary require global-isel from tests	2020-06-15 16:35:18 +02:00
test_g_brjt.mir
test_g_build_vector_trunc.mir
test_g_build_vector.mir
test_g_concat_vectors.mir
test_g_constant.mir
test_g_dyn_stackalloc.mir
test_g_extract.mir
test_g_fcmp.mir
test_g_fconstant.mir
test_g_icmp.mir
test_g_insert.mir
test_g_intrinsic_w_side_effects.mir
test_g_intrinsic.mir
test_g_inttoptr.mir
test_g_jump_table.mir
test_g_load.mir
test_g_merge_values.mir
test_g_phi.mir
test_g_ptr_add.mir
test_g_ptrmask.mir
test_g_ptrtoint.mir
test_g_select.mir
test_g_sext_inreg.mir
test_g_sextload.mir
test_g_shuffle_vector.mir
test_g_store.mir
test_g_trunc.mir
test_g_zextload.mir
test_memccpy_intrinsics.mir
test_phis_precede_nonphis.mir
verifier-generic-extend-truncate.mir
verifier-generic-types-1.mir
verifier-generic-types-2.mir
verifier-implicit-virtreg-invalid-physreg-liveness.mir
verifier-phi-fail0.mir
verifier-phi.mir
verifier-pseudo-terminators.mir
verify-regbankselected.mir
verify-regops.mir
verify-selected.mir