mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-21 03:53:04 +02:00
d8d28772c9
Summary: [GlobalISel][X86] Add support for f32/f64 and vector types in RegisterBank and InstructionSelector. Reviewers: delena, zvi Reviewed By: zvi Subscribers: dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30533 llvm-svn: 296856
90 lines
2.2 KiB
C++
90 lines
2.2 KiB
C++
//===- X86LegalizerInfo.cpp --------------------------------------*- C++ -*-==//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
/// \file
|
|
/// This file implements the targeting of the Machinelegalizer class for X86.
|
|
/// \todo This should be generated by TableGen.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "X86LegalizerInfo.h"
|
|
#include "X86Subtarget.h"
|
|
#include "llvm/CodeGen/ValueTypes.h"
|
|
#include "llvm/IR/DerivedTypes.h"
|
|
#include "llvm/IR/Type.h"
|
|
#include "llvm/Target/TargetOpcodes.h"
|
|
|
|
using namespace llvm;
|
|
using namespace TargetOpcode;
|
|
|
|
#ifndef LLVM_BUILD_GLOBAL_ISEL
|
|
#error "You shouldn't build this"
|
|
#endif
|
|
|
|
X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI) : Subtarget(STI) {
|
|
|
|
setLegalizerInfo32bit();
|
|
setLegalizerInfo64bit();
|
|
setLegalizerInfoSSE1();
|
|
setLegalizerInfoSSE2();
|
|
|
|
computeTables();
|
|
}
|
|
|
|
void X86LegalizerInfo::setLegalizerInfo32bit() {
|
|
|
|
const LLT s8 = LLT::scalar(8);
|
|
const LLT s16 = LLT::scalar(16);
|
|
const LLT s32 = LLT::scalar(32);
|
|
|
|
for (auto Ty : {s8, s16, s32}) {
|
|
setAction({G_ADD, Ty}, Legal);
|
|
setAction({G_SUB, Ty}, Legal);
|
|
}
|
|
}
|
|
|
|
void X86LegalizerInfo::setLegalizerInfo64bit() {
|
|
|
|
if (!Subtarget.is64Bit())
|
|
return;
|
|
|
|
const LLT s64 = LLT::scalar(64);
|
|
|
|
setAction({G_ADD, s64}, Legal);
|
|
setAction({G_SUB, s64}, Legal);
|
|
}
|
|
|
|
void X86LegalizerInfo::setLegalizerInfoSSE1() {
|
|
if (!Subtarget.hasSSE1())
|
|
return;
|
|
|
|
const LLT s32 = LLT::scalar(32);
|
|
const LLT v4s32 = LLT::vector(4, 32);
|
|
|
|
for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
|
|
for (auto Ty : {s32, v4s32})
|
|
setAction({BinOp, Ty}, Legal);
|
|
}
|
|
|
|
void X86LegalizerInfo::setLegalizerInfoSSE2() {
|
|
if (!Subtarget.hasSSE2())
|
|
return;
|
|
|
|
const LLT s64 = LLT::scalar(64);
|
|
const LLT v4s32 = LLT::vector(4, 32);
|
|
const LLT v2s64 = LLT::vector(2, 64);
|
|
|
|
for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
|
|
for (auto Ty : {s64, v2s64})
|
|
setAction({BinOp, Ty}, Legal);
|
|
|
|
for (unsigned BinOp : {G_ADD, G_SUB})
|
|
for (auto Ty : {v4s32})
|
|
setAction({BinOp, Ty}, Legal);
|
|
|
|
}
|