Fraser Cormack be68e4ef95 [RISCV] Expand unaligned fixed-length vector memory accesses ... RVV vectors must be aligned to their element types, so anything less is unaligned. For regular loads and stores, our custom-lowering of fixed-length vectors meant that we opted out of LegalizeDAG's built-in unaligned expansion. This patch adds that logic in to our custom lower function. For masked intrinsics, we declare that anything unaligned is not legal, leaving the ScalarizeMaskedMemIntrin pass to do the expansion for us. Note that neither of these methods can handle the expansion of scalable-vector memory ops, so those cases are left alone by this patch. Scalable loads and stores already go through expansion by default but hit an assertion, and scalable masked intrinsics will silently generate incorrect code. It may be prudent to return an error in both of these cases. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D102493		2021-06-02 09:27:44 +01:00
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fixed-vector-gather.ll	[RISCV] Expand unaligned fixed-length vector memory accesses	2021-06-02 09:27:44 +01:00
fixed-vector-scatter.ll	[RISCV] Expand unaligned fixed-length vector memory accesses	2021-06-02 09:27:44 +01:00
gep.ll
lit.local.cfg
logicalop.ll
reduce-and.ll	[Cost]Canonicalize the cost for logical or/and reductions.	2021-03-19 11:01:58 -07:00
reduce-or.ll	[Cost]Canonicalize the cost for logical or/and reductions.	2021-03-19 11:01:58 -07:00