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438a9a1367
Clang is now providing intrinsics for these and so we need to support them in the backend. Radar 8068427. llvm-svn: 121902
41 lines
1.8 KiB
ArmAsm
41 lines
1.8 KiB
ArmAsm
@ RUN: llvm-mc -mcpu=cortex-a9 -triple thumb-unknown-unknown -show-encoding < %s | FileCheck %s
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.code 16
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@ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
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vcvt.s32.f32 d16, d16
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@ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07]
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vcvt.u32.f32 d16, d16
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@ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
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vcvt.f32.s32 d16, d16
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@ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06]
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vcvt.f32.u32 d16, d16
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@ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
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vcvt.s32.f32 q8, q8
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@ CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xfb,0xff,0xe0,0x07]
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vcvt.u32.f32 q8, q8
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@ CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x06]
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vcvt.f32.s32 q8, q8
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@ CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xfb,0xff,0xe0,0x06]
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vcvt.f32.u32 q8, q8
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@ CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0xff,0xef,0x30,0x0f]
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vcvt.s32.f32 d16, d16, #1
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@ CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0xff,0xff,0x30,0x0f]
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vcvt.u32.f32 d16, d16, #1
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@ CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0xff,0xef,0x30,0x0e]
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vcvt.f32.s32 d16, d16, #1
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@ CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0xff,0xff,0x30,0x0e]
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vcvt.f32.u32 d16, d16, #1
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@ CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0xff,0xef,0x70,0x0f]
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vcvt.s32.f32 q8, q8, #1
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@ CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0xff,0xff,0x70,0x0f]
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vcvt.u32.f32 q8, q8, #1
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@ CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0xff,0xef,0x70,0x0e]
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vcvt.f32.s32 q8, q8, #1
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@ CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0xff,0xff,0x70,0x0e]
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vcvt.f32.u32 q8, q8, #1
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@ CHECK: vcvt.f32.f16 q8, d16 @ encoding: [0xf6,0xff,0x20,0x07]
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vcvt.f32.f16 q8, d16
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@ CHECK: vcvt.f16.f32 d16, q8 @ encoding: [0xf6,0xff,0x20,0x06]
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vcvt.f16.f32 d16, q8
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