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308 lines
12 KiB
C++
308 lines
12 KiB
C++
//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes an abstract interface used to get information about a
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// target machines register file. This information is used for a variety of
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// purposed, especially register allocation.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MC_MCREGISTERINFO_H
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#define LLVM_MC_MCREGISTERINFO_H
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#include "llvm/ADT/DenseMap.h"
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#include <cassert>
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namespace llvm {
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/// MCRegisterClass - Base class of TargetRegisterClass.
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class MCRegisterClass {
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public:
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typedef const unsigned* iterator;
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typedef const unsigned* const_iterator;
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private:
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unsigned ID;
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const char *Name;
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const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
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const int CopyCost;
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const bool Allocatable;
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const iterator RegsBegin, RegsEnd;
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const unsigned char *const RegSet;
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const unsigned RegSetSize;
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public:
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MCRegisterClass(unsigned id, const char *name,
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unsigned RS, unsigned Al, int CC, bool Allocable,
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iterator RB, iterator RE, const unsigned char *Bits,
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unsigned NumBytes)
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: ID(id), Name(name), RegSize(RS), Alignment(Al), CopyCost(CC),
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Allocatable(Allocable), RegsBegin(RB), RegsEnd(RE), RegSet(Bits),
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RegSetSize(NumBytes) {
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for (iterator i = RegsBegin; i != RegsEnd; ++i)
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assert(contains(*i) && "Bit field corrupted.");
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}
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/// getID() - Return the register class ID number.
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///
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unsigned getID() const { return ID; }
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/// getName() - Return the register class name for debugging.
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///
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const char *getName() const { return Name; }
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/// begin/end - Return all of the registers in this class.
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///
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iterator begin() const { return RegsBegin; }
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iterator end() const { return RegsEnd; }
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/// getNumRegs - Return the number of registers in this class.
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///
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unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
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/// getRegister - Return the specified register in the class.
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///
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unsigned getRegister(unsigned i) const {
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assert(i < getNumRegs() && "Register number out of range!");
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return RegsBegin[i];
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}
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/// contains - Return true if the specified register is included in this
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/// register class. This does not include virtual registers.
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bool contains(unsigned Reg) const {
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unsigned InByte = Reg % 8;
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unsigned Byte = Reg / 8;
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if (Byte >= RegSetSize)
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return false;
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return (RegSet[Byte] & (1 << InByte)) != 0;
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}
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/// contains - Return true if both registers are in this class.
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bool contains(unsigned Reg1, unsigned Reg2) const {
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return contains(Reg1) && contains(Reg2);
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}
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/// getSize - Return the size of the register in bytes, which is also the size
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/// of a stack slot allocated to hold a spilled copy of this register.
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unsigned getSize() const { return RegSize; }
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/// getAlignment - Return the minimum required alignment for a register of
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/// this class.
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unsigned getAlignment() const { return Alignment; }
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/// getCopyCost - Return the cost of copying a value between two registers in
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/// this class. A negative number means the register class is very expensive
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/// to copy e.g. status flag register classes.
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int getCopyCost() const { return CopyCost; }
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/// isAllocatable - Return true if this register class may be used to create
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/// virtual registers.
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bool isAllocatable() const { return Allocatable; }
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};
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/// MCRegisterDesc - This record contains all of the information known about
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/// a particular register. The Overlaps field contains a pointer to a zero
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/// terminated array of registers that this register aliases, starting with
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/// itself. This is needed for architectures like X86 which have AL alias AX
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/// alias EAX. The SubRegs field is a zero terminated array of registers that
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/// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
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/// AX. The SuperRegs field is a zero terminated array of registers that are
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/// super-registers of the specific register, e.g. RAX, EAX, are super-registers
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/// of AX.
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///
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struct MCRegisterDesc {
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const char *Name; // Printable name for the reg (for debugging)
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const unsigned *Overlaps; // Overlapping registers, described above
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const unsigned *SubRegs; // Sub-register set, described above
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const unsigned *SuperRegs; // Super-register set, described above
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};
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/// MCRegisterInfo base class - We assume that the target defines a static
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/// array of MCRegisterDesc objects that represent all of the machine
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/// registers that the target has. As such, we simply have to track a pointer
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/// to this array so that we can turn register number into a register
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/// descriptor.
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///
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/// Note this class is designed to be a base class of TargetRegisterInfo, which
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/// is the interface used by codegen. However, specific targets *should never*
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/// specialize this class. MCRegisterInfo should only contain getters to access
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/// TableGen generated physical register data. It must not be extended with
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/// virtual methods.
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///
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class MCRegisterInfo {
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public:
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typedef const MCRegisterClass *regclass_iterator;
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private:
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const MCRegisterDesc *Desc; // Pointer to the descriptor array
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unsigned NumRegs; // Number of entries in the array
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unsigned RAReg; // Return address register
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const MCRegisterClass *Classes; // Pointer to the regclass array
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unsigned NumClasses; // Number of entries in the array
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DenseMap<unsigned, int> L2DwarfRegs; // LLVM to Dwarf regs mapping
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DenseMap<unsigned, int> EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
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DenseMap<unsigned, unsigned> Dwarf2LRegs; // Dwarf to LLVM regs mapping
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DenseMap<unsigned, unsigned> EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
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DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
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public:
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/// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
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/// auto-generated routines. *DO NOT USE*.
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void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
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const MCRegisterClass *C, unsigned NC) {
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Desc = D;
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NumRegs = NR;
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RAReg = RA;
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Classes = C;
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NumClasses = NC;
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}
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/// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf
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/// register number mapping. Called by TableGen auto-generated routines.
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/// *DO NOT USE*.
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void mapLLVMRegToDwarfReg(unsigned LLVMReg, int DwarfReg, bool isEH) {
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if (isEH)
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EHL2DwarfRegs[LLVMReg] = DwarfReg;
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else
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L2DwarfRegs[LLVMReg] = DwarfReg;
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}
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/// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM
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/// register number mapping. Called by TableGen auto-generated routines.
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/// *DO NOT USE*.
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void mapDwarfRegToLLVMReg(unsigned DwarfReg, unsigned LLVMReg, bool isEH) {
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if (isEH)
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EHDwarf2LRegs[DwarfReg] = LLVMReg;
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else
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Dwarf2LRegs[DwarfReg] = LLVMReg;
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}
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/// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
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/// number mapping. By default the SEH register number is just the same
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/// as the LLVM register number.
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/// FIXME: TableGen these numbers. Currently this requires target specific
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/// initialization code.
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void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
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L2SEHRegs[LLVMReg] = SEHReg;
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}
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/// getRARegister - This method should return the register where the return
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/// address can be found.
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unsigned getRARegister() const {
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return RAReg;
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}
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const MCRegisterDesc &operator[](unsigned RegNo) const {
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assert(RegNo < NumRegs &&
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"Attempting to access record for invalid register number!");
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return Desc[RegNo];
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}
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/// Provide a get method, equivalent to [], but more useful if we have a
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/// pointer to this object.
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///
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const MCRegisterDesc &get(unsigned RegNo) const {
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return operator[](RegNo);
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}
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/// getAliasSet - Return the set of registers aliased by the specified
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/// register, or a null list of there are none. The list returned is zero
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/// terminated.
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///
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const unsigned *getAliasSet(unsigned RegNo) const {
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// The Overlaps set always begins with Reg itself.
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return get(RegNo).Overlaps + 1;
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}
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/// getOverlaps - Return a list of registers that overlap Reg, including
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/// itself. This is the same as the alias set except Reg is included in the
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/// list.
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/// These are exactly the registers in { x | regsOverlap(x, Reg) }.
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///
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const unsigned *getOverlaps(unsigned RegNo) const {
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return get(RegNo).Overlaps;
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}
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/// getSubRegisters - Return the list of registers that are sub-registers of
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/// the specified register, or a null list of there are none. The list
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/// returned is zero terminated and sorted according to super-sub register
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/// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
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///
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const unsigned *getSubRegisters(unsigned RegNo) const {
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return get(RegNo).SubRegs;
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}
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/// getSuperRegisters - Return the list of registers that are super-registers
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/// of the specified register, or a null list of there are none. The list
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/// returned is zero terminated and sorted according to super-sub register
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/// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
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///
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const unsigned *getSuperRegisters(unsigned RegNo) const {
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return get(RegNo).SuperRegs;
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}
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/// getName - Return the human-readable symbolic target-specific name for the
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/// specified physical register.
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const char *getName(unsigned RegNo) const {
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return get(RegNo).Name;
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}
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/// getNumRegs - Return the number of registers this target has (useful for
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/// sizing arrays holding per register information)
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unsigned getNumRegs() const {
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return NumRegs;
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}
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/// getDwarfRegNum - Map a target register to an equivalent dwarf register
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/// number. Returns -1 if there is no equivalent value. The second
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/// parameter allows targets to use different numberings for EH info and
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/// debugging info.
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int getDwarfRegNum(unsigned RegNum, bool isEH) const {
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const DenseMap<unsigned, int> &M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
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const DenseMap<unsigned, int>::const_iterator I = M.find(RegNum);
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if (I == M.end()) return -1;
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return I->second;
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}
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/// getLLVMRegNum - Map a dwarf register back to a target register.
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///
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int getLLVMRegNum(unsigned RegNum, bool isEH) const {
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const DenseMap<unsigned, unsigned> &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
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const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum);
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if (I == M.end()) {
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assert(0 && "Invalid RegNum");
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return -1;
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}
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return I->second;
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}
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/// getSEHRegNum - Map a target register to an equivalent SEH register
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/// number. Returns LLVM register number if there is no equivalent value.
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int getSEHRegNum(unsigned RegNum) const {
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const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum);
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if (I == L2SEHRegs.end()) return (int)RegNum;
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return I->second;
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}
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regclass_iterator regclass_begin() const { return Classes; }
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regclass_iterator regclass_end() const { return Classes+NumClasses; }
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unsigned getNumRegClasses() const {
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return (unsigned)(regclass_end()-regclass_begin());
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}
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/// getRegClass - Returns the register class associated with the enumeration
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/// value. See class MCOperandInfo.
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const MCRegisterClass getRegClass(unsigned i) const {
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assert(i < getNumRegClasses() && "Register Class ID out of range");
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return Classes[i];
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}
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};
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} // End llvm namespace
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#endif
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