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bb3ea20b55
Planning to add support for named vregs. This puts is in a conundrum since physregs are named as well. To rectify this we need to use a sigil other than '%' for physregs in MIR. We've settled on using '$' for physregs but first we must repurpose it from external symbols using it, which is what this commit is all about. We think '&' will have familiar semantics for C/C++ users. llvm-svn: 322146
25 lines
517 B
YAML
25 lines
517 B
YAML
# RUN: not llc -march=nvptx -mcpu=sm_20 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
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--- |
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define float @test(float %k) {
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entry:
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%0 = fadd float %k, 3.250000e+00
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ret float %0
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}
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...
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---
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name: test
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registers:
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- { id: 0, class: float32regs }
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- { id: 1, class: float32regs }
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body: |
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bb.0.entry:
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%0 = LD_f32_avar 0, 4, 1, 2, 32, &test_param_0
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; CHECK: [[@LINE+1]]:33: expected a floating point literal
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%1 = FADD_rnf32ri %0, float 3
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StoreRetvalF32 %1, 0
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Return
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...
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