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d654e7d40c
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
16 lines
511 B
LLVM
16 lines
511 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
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; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin | FileCheck %s
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define i64 @fold_load(i64* %a, i64 %b) {
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; CHECK-LABEL: fold_load:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: addq (%rdi), %rax
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; CHECK-NEXT: retq
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%1 = load i64, i64* %a, align 8
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%2 = add i64 %1, %b
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ret i64 %2
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}
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