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e01dc73ad2
All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
247 lines
9.0 KiB
C++
247 lines
9.0 KiB
C++
//===- MachineInstrTest.cpp -----------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/TargetSelect.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "gtest/gtest.h"
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using namespace llvm;
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namespace {
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// Add a few Bogus backend classes so we can create MachineInstrs without
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// depending on a real target.
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class BogusTargetLowering : public TargetLowering {
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public:
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BogusTargetLowering(TargetMachine &TM) : TargetLowering(TM) {}
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};
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class BogusFrameLowering : public TargetFrameLowering {
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public:
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BogusFrameLowering()
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: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 4) {}
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void emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const override {}
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void emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const override {}
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bool hasFP(const MachineFunction &MF) const override { return false; }
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};
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class BogusSubtarget : public TargetSubtargetInfo {
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public:
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BogusSubtarget(TargetMachine &TM)
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: TargetSubtargetInfo(Triple(""), "", "", {}, {}, nullptr, nullptr,
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nullptr, nullptr, nullptr, nullptr, nullptr),
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FL(), TL(TM) {}
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~BogusSubtarget() override {}
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const TargetFrameLowering *getFrameLowering() const override { return &FL; }
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const TargetLowering *getTargetLowering() const override { return &TL; }
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const TargetInstrInfo *getInstrInfo() const override { return &TII; }
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private:
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BogusFrameLowering FL;
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BogusTargetLowering TL;
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TargetInstrInfo TII;
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};
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class BogusTargetMachine : public LLVMTargetMachine {
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public:
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BogusTargetMachine()
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: LLVMTargetMachine(Target(), "", Triple(""), "", "", TargetOptions(),
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Reloc::Static, CodeModel::Small, CodeGenOpt::Default),
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ST(*this) {}
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~BogusTargetMachine() override {}
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const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override {
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return &ST;
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}
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private:
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BogusSubtarget ST;
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};
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std::unique_ptr<BogusTargetMachine> createTargetMachine() {
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return llvm::make_unique<BogusTargetMachine>();
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}
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std::unique_ptr<MachineFunction> createMachineFunction() {
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LLVMContext Ctx;
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Module M("Module", Ctx);
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auto Type = FunctionType::get(Type::getVoidTy(Ctx), false);
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auto F = Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &M);
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auto TM = createTargetMachine();
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unsigned FunctionNum = 42;
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MachineModuleInfo MMI(TM.get());
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return llvm::make_unique<MachineFunction>(F, *TM, FunctionNum, MMI);
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}
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// This test makes sure that MachineInstr::isIdenticalTo handles Defs correctly
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// for various combinations of IgnoreDefs, and also that it is symmetrical.
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TEST(IsIdenticalToTest, DifferentDefs) {
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auto MF = createMachineFunction();
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unsigned short NumOps = 2;
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unsigned char NumDefs = 1;
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MCOperandInfo OpInfo[] = {
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{0, 0, MCOI::OPERAND_REGISTER, 0},
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{0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
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MCInstrDesc MCID = {
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0, NumOps, NumDefs, 0, 0, 1ULL << MCID::HasOptionalDef,
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0, nullptr, nullptr, OpInfo, 0, nullptr};
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// Create two MIs with different virtual reg defs and the same uses.
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unsigned VirtualDef1 = -42; // The value doesn't matter, but the sign does.
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unsigned VirtualDef2 = -43;
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unsigned VirtualUse = -44;
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auto MI1 = MF->CreateMachineInstr(MCID, DebugLoc());
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MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
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auto MI2 = MF->CreateMachineInstr(MCID, DebugLoc());
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MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
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// Check that they are identical when we ignore virtual register defs, but not
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// when we check defs.
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ASSERT_FALSE(MI1->isIdenticalTo(*MI2, MachineInstr::CheckDefs));
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ASSERT_FALSE(MI2->isIdenticalTo(*MI1, MachineInstr::CheckDefs));
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ASSERT_TRUE(MI1->isIdenticalTo(*MI2, MachineInstr::IgnoreVRegDefs));
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ASSERT_TRUE(MI2->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs));
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// Create two MIs with different virtual reg defs, and a def or use of a
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// sentinel register.
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unsigned SentinelReg = 0;
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auto MI3 = MF->CreateMachineInstr(MCID, DebugLoc());
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MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
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auto MI4 = MF->CreateMachineInstr(MCID, DebugLoc());
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MI4->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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MI4->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
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// Check that they are never identical.
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ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::CheckDefs));
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ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::CheckDefs));
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ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::IgnoreVRegDefs));
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ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::IgnoreVRegDefs));
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}
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// Check that MachineInstrExpressionTrait::isEqual is symmetric and in sync with
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// MachineInstrExpressionTrait::getHashValue
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void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) {
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bool IsEqual1 = MachineInstrExpressionTrait::isEqual(MI1, MI2);
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bool IsEqual2 = MachineInstrExpressionTrait::isEqual(MI2, MI1);
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ASSERT_EQ(IsEqual1, IsEqual2);
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auto Hash1 = MachineInstrExpressionTrait::getHashValue(MI1);
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auto Hash2 = MachineInstrExpressionTrait::getHashValue(MI2);
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ASSERT_EQ(IsEqual1, Hash1 == Hash2);
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}
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// This test makes sure that MachineInstrExpressionTraits::isEqual is in sync
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// with MachineInstrExpressionTraits::getHashValue.
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TEST(MachineInstrExpressionTraitTest, IsEqualAgreesWithGetHashValue) {
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auto MF = createMachineFunction();
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unsigned short NumOps = 2;
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unsigned char NumDefs = 1;
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MCOperandInfo OpInfo[] = {
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{0, 0, MCOI::OPERAND_REGISTER, 0},
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{0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
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MCInstrDesc MCID = {
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0, NumOps, NumDefs, 0, 0, 1ULL << MCID::HasOptionalDef,
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0, nullptr, nullptr, OpInfo, 0, nullptr};
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// Define a series of instructions with different kinds of operands and make
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// sure that the hash function is consistent with isEqual for various
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// combinations of them.
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unsigned VirtualDef1 = -42;
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unsigned VirtualDef2 = -43;
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unsigned VirtualReg = -44;
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unsigned SentinelReg = 0;
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unsigned PhysicalReg = 45;
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auto VD1VU = MF->CreateMachineInstr(MCID, DebugLoc());
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VD1VU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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VD1VU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
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auto VD2VU = MF->CreateMachineInstr(MCID, DebugLoc());
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VD2VU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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VD2VU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
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auto VD1SU = MF->CreateMachineInstr(MCID, DebugLoc());
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VD1SU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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VD1SU->addOperand(*MF,
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MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
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auto VD1SD = MF->CreateMachineInstr(MCID, DebugLoc());
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VD1SD->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
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VD1SD->addOperand(*MF,
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MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
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auto VD2PU = MF->CreateMachineInstr(MCID, DebugLoc());
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VD2PU->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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VD2PU->addOperand(*MF,
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MachineOperand::CreateReg(PhysicalReg, /*isDef*/ false));
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auto VD2PD = MF->CreateMachineInstr(MCID, DebugLoc());
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VD2PD->addOperand(*MF,
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MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
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VD2PD->addOperand(*MF,
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MachineOperand::CreateReg(PhysicalReg, /*isDef*/ true));
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checkHashAndIsEqualMatch(VD1VU, VD2VU);
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checkHashAndIsEqualMatch(VD1VU, VD1SU);
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checkHashAndIsEqualMatch(VD1VU, VD1SD);
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checkHashAndIsEqualMatch(VD1VU, VD2PU);
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checkHashAndIsEqualMatch(VD1VU, VD2PD);
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checkHashAndIsEqualMatch(VD2VU, VD1SU);
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checkHashAndIsEqualMatch(VD2VU, VD1SD);
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checkHashAndIsEqualMatch(VD2VU, VD2PU);
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checkHashAndIsEqualMatch(VD2VU, VD2PD);
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checkHashAndIsEqualMatch(VD1SU, VD1SD);
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checkHashAndIsEqualMatch(VD1SU, VD2PU);
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checkHashAndIsEqualMatch(VD1SU, VD2PD);
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checkHashAndIsEqualMatch(VD1SD, VD2PU);
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checkHashAndIsEqualMatch(VD1SD, VD2PD);
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checkHashAndIsEqualMatch(VD2PU, VD2PD);
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}
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} // end namespace
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